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<title>Using as: SCORE-Opts</title>
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<link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<a name="SCORE_002dOpts"></a>
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Next: <a href="SCORE_002dPseudo.html#SCORE_002dPseudo" accesskey="n" rel="next">SCORE-Pseudo</a>, Up: <a href="SCORE_002dDependent.html#SCORE_002dDependent" accesskey="u" rel="up">SCORE-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
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<a name="Options-20"></a>
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<h4 class="subsection">9.39.1 Options</h4>
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<a name="index-options-for-SCORE"></a>
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<a name="index-SCORE-options"></a>
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<a name="index-architectures_002c-SCORE"></a>
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<a name="index-SCORE-architectures"></a>
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<p>The following table lists all available SCORE options.
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</p>
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<dl compact="compact">
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<dt><code>-G <var>num</var></code></dt>
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<dd><p>This option sets the largest size of an object that can be referenced
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implicitly with the <code>gp</code> register. The default value is 8.
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</p>
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</dd>
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<dt><code>-EB</code></dt>
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<dd><p>Assemble code for a big-endian cpu
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</p>
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</dd>
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<dt><code>-EL</code></dt>
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<dd><p>Assemble code for a little-endian cpu
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</p>
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</dd>
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<dt><code>-FIXDD</code></dt>
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<dd><p>Assemble code for fix data dependency
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</p>
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</dd>
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<dt><code>-NWARN</code></dt>
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<dd><p>Assemble code for no warning message for fix data dependency
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</p>
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</dd>
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<dt><code>-SCORE5</code></dt>
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<dd><p>Assemble code for target is SCORE5
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</p>
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</dd>
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<dt><code>-SCORE5U</code></dt>
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<dd><p>Assemble code for target is SCORE5U
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</p>
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</dd>
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<dt><code>-SCORE7</code></dt>
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<dd><p>Assemble code for target is SCORE7, this is default setting
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</p>
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</dd>
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<dt><code>-SCORE3</code></dt>
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<dd><p>Assemble code for target is SCORE3
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</p>
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</dd>
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<dt><code>-march=score7</code></dt>
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<dd><p>Assemble code for target is SCORE7, this is default setting
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</p>
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</dd>
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<dt><code>-march=score3</code></dt>
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<dd><p>Assemble code for target is SCORE3
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</p>
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</dd>
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<dt><code>-USE_R1</code></dt>
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<dd><p>Assemble code for no warning message when using temp register r1
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</p>
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</dd>
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<dt><code>-KPIC</code></dt>
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<dd><p>Generate code for PIC. This option tells the assembler to generate
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score position-independent macro expansions. It also tells the
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assembler to mark the output file as PIC.
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</p>
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</dd>
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<dt><code>-O0</code></dt>
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<dd><p>Assembler will not perform any optimizations
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</p>
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</dd>
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<dt><code>-V</code></dt>
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<dd><p>Sunplus release version
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</p>
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</dd>
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</dl>
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