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<title>Using as: M68HC11-Opts</title>
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<a name="M68HC11_002dOpts"></a>
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<div class="header">
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<p>
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Next: <a href="M68HC11_002dSyntax.html#M68HC11_002dSyntax" accesskey="n" rel="next">M68HC11-Syntax</a>, Up: <a href="M68HC11_002dDependent.html#M68HC11_002dDependent" accesskey="u" rel="up">M68HC11-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="M68HC11-and-M68HC12-Options"></a>
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<h4 class="subsection">9.24.1 M68HC11 and M68HC12 Options</h4>
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<a name="index-options_002c-M68HC11"></a>
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<a name="index-M68HC11-options"></a>
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<p>The Motorola 68HC11 and 68HC12 version of <code>as</code> have a few machine
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dependent options.
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</p>
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<dl compact="compact">
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<dd>
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<a name="index-_002dm68hc11"></a>
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</dd>
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<dt><code>-m68hc11</code></dt>
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<dd><p>This option switches the assembler into the M68HC11 mode. In this mode,
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the assembler only accepts 68HC11 operands and mnemonics. It produces
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code for the 68HC11.
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</p>
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<a name="index-_002dm68hc12"></a>
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</dd>
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<dt><code>-m68hc12</code></dt>
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<dd><p>This option switches the assembler into the M68HC12 mode. In this mode,
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the assembler also accepts 68HC12 operands and mnemonics. It produces
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code for the 68HC12. A few 68HC11 instructions are replaced by
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some 68HC12 instructions as recommended by Motorola specifications.
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</p>
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<a name="index-_002dm68hcs12"></a>
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</dd>
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<dt><code>-m68hcs12</code></dt>
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<dd><p>This option switches the assembler into the M68HCS12 mode. This mode is
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similar to ‘<samp>-m68hc12</samp>’ but specifies to assemble for the 68HCS12
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series. The only difference is on the assembling of the ‘<samp>movb</samp>’
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and ‘<samp>movw</samp>’ instruction when a PC-relative operand is used.
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</p>
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<a name="index-_002dmm9s12x"></a>
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</dd>
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<dt><code>-mm9s12x</code></dt>
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<dd><p>This option switches the assembler into the M9S12X mode. This mode is
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similar to ‘<samp>-m68hc12</samp>’ but specifies to assemble for the S12X
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series which is a superset of the HCS12.
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</p>
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<a name="index-_002dmm9s12xg"></a>
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</dd>
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<dt><code>-mm9s12xg</code></dt>
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<dd><p>This option switches the assembler into the XGATE mode for the RISC
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co-processor featured on some S12X-family chips.
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</p>
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<a name="index-_002d_002dxgate_002dramoffset"></a>
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</dd>
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<dt><code>--xgate-ramoffset</code></dt>
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<dd><p>This option instructs the linker to offset RAM addresses from S12X address
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space into XGATE address space.
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</p>
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<a name="index-_002dmshort"></a>
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</dd>
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<dt><code>-mshort</code></dt>
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<dd><p>This option controls the ABI and indicates to use a 16-bit integer ABI.
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It has no effect on the assembled instructions.
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This is the default.
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</p>
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<a name="index-_002dmlong"></a>
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</dd>
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<dt><code>-mlong</code></dt>
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<dd><p>This option controls the ABI and indicates to use a 32-bit integer ABI.
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</p>
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<a name="index-_002dmshort_002ddouble"></a>
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</dd>
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<dt><code>-mshort-double</code></dt>
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<dd><p>This option controls the ABI and indicates to use a 32-bit float ABI.
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This is the default.
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</p>
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<a name="index-_002dmlong_002ddouble"></a>
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</dd>
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<dt><code>-mlong-double</code></dt>
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<dd><p>This option controls the ABI and indicates to use a 64-bit float ABI.
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</p>
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<a name="index-_002d_002dstrict_002ddirect_002dmode"></a>
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</dd>
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<dt><code>--strict-direct-mode</code></dt>
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<dd><p>You can use the ‘<samp>--strict-direct-mode</samp>’ option to disable
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the automatic translation of direct page mode addressing into
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extended mode when the instruction does not support direct mode.
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For example, the ‘<samp>clr</samp>’ instruction does not support direct page
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mode addressing. When it is used with the direct page mode,
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<code>as</code> will ignore it and generate an absolute addressing.
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This option prevents <code>as</code> from doing this, and the wrong
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usage of the direct page mode will raise an error.
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</p>
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<a name="index-_002d_002dshort_002dbranches"></a>
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</dd>
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<dt><code>--short-branches</code></dt>
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<dd><p>The ‘<samp>--short-branches</samp>’ option turns off the translation of
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relative branches into absolute branches when the branch offset is
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out of range. By default <code>as</code> transforms the relative
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branch (‘<samp>bsr</samp>’, ‘<samp>bgt</samp>’, ‘<samp>bge</samp>’, ‘<samp>beq</samp>’, ‘<samp>bne</samp>’,
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‘<samp>ble</samp>’, ‘<samp>blt</samp>’, ‘<samp>bhi</samp>’, ‘<samp>bcc</samp>’, ‘<samp>bls</samp>’,
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‘<samp>bcs</samp>’, ‘<samp>bmi</samp>’, ‘<samp>bvs</samp>’, ‘<samp>bvs</samp>’, ‘<samp>bra</samp>’) into
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an absolute branch when the offset is out of the -128 .. 127 range.
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In that case, the ‘<samp>bsr</samp>’ instruction is translated into a
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‘<samp>jsr</samp>’, the ‘<samp>bra</samp>’ instruction is translated into a
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‘<samp>jmp</samp>’ and the conditional branches instructions are inverted and
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followed by a ‘<samp>jmp</samp>’. This option disables these translations
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and <code>as</code> will generate an error if a relative branch
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is out of range. This option does not affect the optimization
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associated to the ‘<samp>jbra</samp>’, ‘<samp>jbsr</samp>’ and ‘<samp>jbXX</samp>’ pseudo opcodes.
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</p>
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<a name="index-_002d_002dforce_002dlong_002dbranches"></a>
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</dd>
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<dt><code>--force-long-branches</code></dt>
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<dd><p>The ‘<samp>--force-long-branches</samp>’ option forces the translation of
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relative branches into absolute branches. This option does not affect
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the optimization associated to the ‘<samp>jbra</samp>’, ‘<samp>jbsr</samp>’ and
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‘<samp>jbXX</samp>’ pseudo opcodes.
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</p>
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<a name="index-_002d_002dprint_002dinsn_002dsyntax"></a>
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</dd>
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<dt><code>--print-insn-syntax</code></dt>
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<dd><p>You can use the ‘<samp>--print-insn-syntax</samp>’ option to obtain the
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syntax description of the instruction when an error is detected.
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</p>
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<a name="index-_002d_002dprint_002dopcodes"></a>
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</dd>
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<dt><code>--print-opcodes</code></dt>
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<dd><p>The ‘<samp>--print-opcodes</samp>’ option prints the list of all the
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instructions with their syntax. The first item of each line
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represents the instruction name and the rest of the line indicates
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the possible operands for that instruction. The list is printed
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in alphabetical order. Once the list is printed <code>as</code>
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exits.
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</p>
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<a name="index-_002d_002dgenerate_002dexample"></a>
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</dd>
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<dt><code>--generate-example</code></dt>
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<dd><p>The ‘<samp>--generate-example</samp>’ option is similar to ‘<samp>--print-opcodes</samp>’
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but it generates an example for each instruction instead.
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</p></dd>
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</dl>
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<hr>
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<div class="header">
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<p>
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Next: <a href="M68HC11_002dSyntax.html#M68HC11_002dSyntax" accesskey="n" rel="next">M68HC11-Syntax</a>, Up: <a href="M68HC11_002dDependent.html#M68HC11_002dDependent" accesskey="u" rel="up">M68HC11-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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