<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
|
<html>
|
<!-- Copyright (C) 1988-2021 Free Software Foundation, Inc.
|
|
Permission is granted to copy, distribute and/or modify this document
|
under the terms of the GNU Free Documentation License, Version 1.3 or
|
any later version published by the Free Software Foundation; with the
|
Invariant Sections being "Free Software" and "Free Software Needs
|
Free Documentation", with the Front-Cover Texts being "A GNU Manual,"
|
and with the Back-Cover Texts as in (a) below.
|
|
(a) The FSF's Back-Cover Text is: "You are free to copy and modify
|
this GNU Manual. Buying copies from GNU Press supports the FSF in
|
developing GNU and promoting software freedom." -->
|
<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ -->
|
<head>
|
<title>Debugging with GDB: PowerPC Features</title>
|
|
<meta name="description" content="Debugging with GDB: PowerPC Features">
|
<meta name="keywords" content="Debugging with GDB: PowerPC Features">
|
<meta name="resource-type" content="document">
|
<meta name="distribution" content="global">
|
<meta name="Generator" content="makeinfo">
|
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
|
<link href="index.html#Top" rel="start" title="Top">
|
<link href="Concept-Index.html#Concept-Index" rel="index" title="Concept Index">
|
<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
|
<link href="Standard-Target-Features.html#Standard-Target-Features" rel="up" title="Standard Target Features">
|
<link href="RISC_002dV-Features.html#RISC_002dV-Features" rel="next" title="RISC-V Features">
|
<link href="OpenRISC-1000-Features.html#OpenRISC-1000-Features" rel="previous" title="OpenRISC 1000 Features">
|
<style type="text/css">
|
<!--
|
a.summary-letter {text-decoration: none}
|
blockquote.smallquotation {font-size: smaller}
|
div.display {margin-left: 3.2em}
|
div.example {margin-left: 3.2em}
|
div.indentedblock {margin-left: 3.2em}
|
div.lisp {margin-left: 3.2em}
|
div.smalldisplay {margin-left: 3.2em}
|
div.smallexample {margin-left: 3.2em}
|
div.smallindentedblock {margin-left: 3.2em; font-size: smaller}
|
div.smalllisp {margin-left: 3.2em}
|
kbd {font-style:oblique}
|
pre.display {font-family: inherit}
|
pre.format {font-family: inherit}
|
pre.menu-comment {font-family: serif}
|
pre.menu-preformatted {font-family: serif}
|
pre.smalldisplay {font-family: inherit; font-size: smaller}
|
pre.smallexample {font-size: smaller}
|
pre.smallformat {font-family: inherit; font-size: smaller}
|
pre.smalllisp {font-size: smaller}
|
span.nocodebreak {white-space:nowrap}
|
span.nolinebreak {white-space:nowrap}
|
span.roman {font-family:serif; font-weight:normal}
|
span.sansserif {font-family:sans-serif; font-weight:normal}
|
ul.no-bullet {list-style: none}
|
-->
|
</style>
|
|
|
</head>
|
|
<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
|
<a name="PowerPC-Features"></a>
|
<div class="header">
|
<p>
|
Next: <a href="RISC_002dV-Features.html#RISC_002dV-Features" accesskey="n" rel="next">RISC-V Features</a>, Previous: <a href="OpenRISC-1000-Features.html#OpenRISC-1000-Features" accesskey="p" rel="previous">OpenRISC 1000 Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
|
</div>
|
<hr>
|
<a name="PowerPC-Features-1"></a>
|
<h4 class="subsection">G.5.11 PowerPC Features</h4>
|
<a name="index-target-descriptions_002c-PowerPC-features"></a>
|
|
<p>The ‘<samp>org.gnu.gdb.power.core</samp>’ feature is required for PowerPC
|
targets. It should contain registers ‘<samp>r0</samp>’ through ‘<samp>r31</samp>’,
|
‘<samp>pc</samp>’, ‘<samp>msr</samp>’, ‘<samp>cr</samp>’, ‘<samp>lr</samp>’, ‘<samp>ctr</samp>’, and
|
‘<samp>xer</samp>’. They may be 32-bit or 64-bit depending on the target.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.fpu</samp>’ feature is optional. It should
|
contain registers ‘<samp>f0</samp>’ through ‘<samp>f31</samp>’ and ‘<samp>fpscr</samp>’.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.altivec</samp>’ feature is optional. It should
|
contain registers ‘<samp>vr0</samp>’ through ‘<samp>vr31</samp>’, ‘<samp>vscr</samp>’, and
|
‘<samp>vrsave</samp>’. <small>GDB</small> will define pseudo-registers ‘<samp>v0</samp>’
|
through ‘<samp>v31</samp>’ as aliases for the corresponding ‘<samp>vrX</samp>’
|
registers.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.vsx</samp>’ feature is optional. It should
|
contain registers ‘<samp>vs0h</samp>’ through ‘<samp>vs31h</samp>’. <small>GDB</small> will
|
combine these registers with the floating point registers (‘<samp>f0</samp>’
|
through ‘<samp>f31</samp>’) and the altivec registers (‘<samp>vr0</samp>’ through
|
‘<samp>vr31</samp>’) to present the 128-bit wide registers ‘<samp>vs0</samp>’ through
|
‘<samp>vs63</samp>’, the set of vector-scalar registers for POWER7.
|
Therefore, this feature requires both ‘<samp>org.gnu.gdb.power.fpu</samp>’ and
|
‘<samp>org.gnu.gdb.power.altivec</samp>’.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.spe</samp>’ feature is optional. It should
|
contain registers ‘<samp>ev0h</samp>’ through ‘<samp>ev31h</samp>’, ‘<samp>acc</samp>’, and
|
‘<samp>spefscr</samp>’. SPE targets should provide 32-bit registers in
|
‘<samp>org.gnu.gdb.power.core</samp>’ and provide the upper halves in
|
‘<samp>ev0h</samp>’ through ‘<samp>ev31h</samp>’. <small>GDB</small> will combine
|
these to present registers ‘<samp>ev0</samp>’ through ‘<samp>ev31</samp>’ to the
|
user.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.ppr</samp>’ feature is optional. It should
|
contain the 64-bit register ‘<samp>ppr</samp>’.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.dscr</samp>’ feature is optional. It should
|
contain the 64-bit register ‘<samp>dscr</samp>’.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.tar</samp>’ feature is optional. It should
|
contain the 64-bit register ‘<samp>tar</samp>’.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.ebb</samp>’ feature is optional. It should
|
contain registers ‘<samp>bescr</samp>’, ‘<samp>ebbhr</samp>’ and ‘<samp>ebbrr</samp>’, all
|
64-bit wide.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.linux.pmu</samp>’ feature is optional. It should
|
contain registers ‘<samp>mmcr0</samp>’, ‘<samp>mmcr2</samp>’, ‘<samp>siar</samp>’, ‘<samp>sdar</samp>’
|
and ‘<samp>sier</samp>’, all 64-bit wide. This is the subset of the isa 2.07
|
server PMU registers provided by <small>GNU</small>/Linux.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.htm.spr</samp>’ feature is optional. It should
|
contain registers ‘<samp>tfhar</samp>’, ‘<samp>texasr</samp>’ and ‘<samp>tfiar</samp>’, all
|
64-bit wide.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.htm.core</samp>’ feature is optional. It should
|
contain the checkpointed general-purpose registers ‘<samp>cr0</samp>’ through
|
‘<samp>cr31</samp>’, as well as the checkpointed registers ‘<samp>clr</samp>’ and
|
‘<samp>cctr</samp>’. These registers may all be either 32-bit or 64-bit
|
depending on the target. It should also contain the checkpointed
|
registers ‘<samp>ccr</samp>’ and ‘<samp>cxer</samp>’, which should both be 32-bit
|
wide.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.htm.fpu</samp>’ feature is optional. It should
|
contain the checkpointed 64-bit floating-point registers ‘<samp>cf0</samp>’
|
through ‘<samp>cf31</samp>’, as well as the checkpointed 64-bit register
|
‘<samp>cfpscr</samp>’.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.htm.altivec</samp>’ feature is optional. It
|
should contain the checkpointed altivec registers ‘<samp>cvr0</samp>’ through
|
‘<samp>cvr31</samp>’, all 128-bit wide. It should also contain the
|
checkpointed registers ‘<samp>cvscr</samp>’ and ‘<samp>cvrsave</samp>’, both 32-bit
|
wide.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.htm.vsx</samp>’ feature is optional. It should
|
contain registers ‘<samp>cvs0h</samp>’ through ‘<samp>cvs31h</samp>’. <small>GDB</small>
|
will combine these registers with the checkpointed floating point
|
registers (‘<samp>cf0</samp>’ through ‘<samp>cf31</samp>’) and the checkpointed
|
altivec registers (‘<samp>cvr0</samp>’ through ‘<samp>cvr31</samp>’) to present the
|
128-bit wide checkpointed vector-scalar registers ‘<samp>cvs0</samp>’ through
|
‘<samp>cvs63</samp>’. Therefore, this feature requires both
|
‘<samp>org.gnu.gdb.power.htm.altivec</samp>’ and
|
‘<samp>org.gnu.gdb.power.htm.fpu</samp>’.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.htm.ppr</samp>’ feature is optional. It should
|
contain the 64-bit checkpointed register ‘<samp>cppr</samp>’.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.htm.dscr</samp>’ feature is optional. It should
|
contain the 64-bit checkpointed register ‘<samp>cdscr</samp>’.
|
</p>
|
<p>The ‘<samp>org.gnu.gdb.power.htm.tar</samp>’ feature is optional. It should
|
contain the 64-bit checkpointed register ‘<samp>ctar</samp>’.
|
</p>
|
|
<hr>
|
<div class="header">
|
<p>
|
Next: <a href="RISC_002dV-Features.html#RISC_002dV-Features" accesskey="n" rel="next">RISC-V Features</a>, Previous: <a href="OpenRISC-1000-Features.html#OpenRISC-1000-Features" accesskey="p" rel="previous">OpenRISC 1000 Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
|
</div>
|
|
|
|
</body>
|
</html>
|
