<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
|
<html>
|
<!-- This file documents the GNU Assembler "as".
|
|
Copyright (C) 1991-2021 Free Software Foundation, Inc.
|
|
Permission is granted to copy, distribute and/or modify this document
|
under the terms of the GNU Free Documentation License, Version 1.3
|
or any later version published by the Free Software Foundation;
|
with no Invariant Sections, with no Front-Cover Texts, and with no
|
Back-Cover Texts. A copy of the license is included in the
|
section entitled "GNU Free Documentation License".
|
-->
|
<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ -->
|
<head>
|
<title>Using as: i386-Mnemonics</title>
|
|
<meta name="description" content="Using as: i386-Mnemonics">
|
<meta name="keywords" content="Using as: i386-Mnemonics">
|
<meta name="resource-type" content="document">
|
<meta name="distribution" content="global">
|
<meta name="Generator" content="makeinfo">
|
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
|
<link href="index.html#Top" rel="start" title="Top">
|
<link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
|
<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
|
<link href="i386_002dDependent.html#i386_002dDependent" rel="up" title="i386-Dependent">
|
<link href="i386_002dRegs.html#i386_002dRegs" rel="next" title="i386-Regs">
|
<link href="i386_002dChars.html#i386_002dChars" rel="previous" title="i386-Chars">
|
<style type="text/css">
|
<!--
|
a.summary-letter {text-decoration: none}
|
blockquote.smallquotation {font-size: smaller}
|
div.display {margin-left: 3.2em}
|
div.example {margin-left: 3.2em}
|
div.indentedblock {margin-left: 3.2em}
|
div.lisp {margin-left: 3.2em}
|
div.smalldisplay {margin-left: 3.2em}
|
div.smallexample {margin-left: 3.2em}
|
div.smallindentedblock {margin-left: 3.2em; font-size: smaller}
|
div.smalllisp {margin-left: 3.2em}
|
kbd {font-style:oblique}
|
pre.display {font-family: inherit}
|
pre.format {font-family: inherit}
|
pre.menu-comment {font-family: serif}
|
pre.menu-preformatted {font-family: serif}
|
pre.smalldisplay {font-family: inherit; font-size: smaller}
|
pre.smallexample {font-size: smaller}
|
pre.smallformat {font-family: inherit; font-size: smaller}
|
pre.smalllisp {font-size: smaller}
|
span.nocodebreak {white-space:nowrap}
|
span.nolinebreak {white-space:nowrap}
|
span.roman {font-family:serif; font-weight:normal}
|
span.sansserif {font-family:sans-serif; font-weight:normal}
|
ul.no-bullet {list-style: none}
|
-->
|
</style>
|
|
|
</head>
|
|
<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
|
<a name="i386_002dMnemonics"></a>
|
<div class="header">
|
<p>
|
Next: <a href="i386_002dRegs.html#i386_002dRegs" accesskey="n" rel="next">i386-Regs</a>, Previous: <a href="i386_002dSyntax.html#i386_002dSyntax" accesskey="p" rel="previous">i386-Syntax</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
|
</div>
|
<hr>
|
<a name="i386_002dMnemonics-1"></a>
|
<h4 class="subsection">9.16.4 i386-Mnemonics</h4>
|
<a name="Instruction-Naming"></a>
|
<h4 class="subsubsection">9.16.4.1 Instruction Naming</h4>
|
|
<a name="index-i386-instruction-naming"></a>
|
<a name="index-instruction-naming_002c-i386"></a>
|
<a name="index-x86_002d64-instruction-naming"></a>
|
<a name="index-instruction-naming_002c-x86_002d64"></a>
|
|
<p>Instruction mnemonics are suffixed with one character modifiers which
|
specify the size of operands. The letters ‘<samp>b</samp>’, ‘<samp>w</samp>’, ‘<samp>l</samp>’
|
and ‘<samp>q</samp>’ specify byte, word, long and quadruple word operands. If
|
no suffix is specified by an instruction then <code>as</code> tries to
|
fill in the missing suffix based on the destination register operand
|
(the last one by convention). Thus, ‘<samp>mov %ax, %bx</samp>’ is equivalent
|
to ‘<samp>movw %ax, %bx</samp>’; also, ‘<samp>mov $1, %bx</samp>’ is equivalent to
|
‘<samp>movw $1, bx</samp>’. Note that this is incompatible with the AT&T Unix
|
assembler which assumes that a missing mnemonic suffix implies long
|
operand size. (This incompatibility does not affect compiler output
|
since compilers always explicitly specify the mnemonic suffix.)
|
</p>
|
<p>When there is no sizing suffix and no (suitable) register operands to
|
deduce the size of memory operands, with a few exceptions and where long
|
operand size is possible in the first place, operand size will default
|
to long in 32- and 64-bit modes. Similarly it will default to short in
|
16-bit mode. Noteworthy exceptions are
|
</p>
|
<ul>
|
<li> Instructions with an implicit on-stack operand as well as branches,
|
which default to quad in 64-bit mode.
|
|
</li><li> Sign- and zero-extending moves, which default to byte size source
|
operands.
|
|
</li><li> Floating point insns with integer operands, which default to short (for
|
perhaps historical reasons).
|
|
</li><li> CRC32 with a 64-bit destination, which defaults to a quad source
|
operand.
|
|
</li></ul>
|
|
<a name="index-encoding-options_002c-i386"></a>
|
<a name="index-encoding-options_002c-x86_002d64"></a>
|
|
<p>Different encoding options can be specified via pseudo prefixes:
|
</p>
|
<ul>
|
<li> ‘<samp>{disp8}</samp>’ – prefer 8-bit displacement.
|
|
</li><li> ‘<samp>{disp32}</samp>’ – prefer 32-bit displacement.
|
|
</li><li> ‘<samp>{disp16}</samp>’ – prefer 16-bit displacement.
|
|
</li><li> ‘<samp>{load}</samp>’ – prefer load-form instruction.
|
|
</li><li> ‘<samp>{store}</samp>’ – prefer store-form instruction.
|
|
</li><li> ‘<samp>{vex}</samp>’ – encode with VEX prefix.
|
|
</li><li> ‘<samp>{vex3}</samp>’ – encode with 3-byte VEX prefix.
|
|
</li><li> ‘<samp>{evex}</samp>’ – encode with EVEX prefix.
|
|
</li><li> ‘<samp>{rex}</samp>’ – prefer REX prefix for integer and legacy vector
|
instructions (x86-64 only). Note that this differs from the ‘<samp>rex</samp>’
|
prefix which generates REX prefix unconditionally.
|
|
</li><li> ‘<samp>{nooptimize}</samp>’ – disable instruction size optimization.
|
</li></ul>
|
|
<p>Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix
|
by default. The pseudo ‘<samp>{vex}</samp>’ prefix can be used to encode
|
mnemonics of Intel VNNI instructions with the VEX prefix.
|
</p>
|
<a name="index-conversion-instructions_002c-i386"></a>
|
<a name="index-i386-conversion-instructions"></a>
|
<a name="index-conversion-instructions_002c-x86_002d64"></a>
|
<a name="index-x86_002d64-conversion-instructions"></a>
|
<p>The Intel-syntax conversion instructions
|
</p>
|
<ul>
|
<li> ‘<samp>cbw</samp>’ — sign-extend byte in ‘<samp>%al</samp>’ to word in ‘<samp>%ax</samp>’,
|
|
</li><li> ‘<samp>cwde</samp>’ — sign-extend word in ‘<samp>%ax</samp>’ to long in ‘<samp>%eax</samp>’,
|
|
</li><li> ‘<samp>cwd</samp>’ — sign-extend word in ‘<samp>%ax</samp>’ to long in ‘<samp>%dx:%ax</samp>’,
|
|
</li><li> ‘<samp>cdq</samp>’ — sign-extend dword in ‘<samp>%eax</samp>’ to quad in ‘<samp>%edx:%eax</samp>’,
|
|
</li><li> ‘<samp>cdqe</samp>’ — sign-extend dword in ‘<samp>%eax</samp>’ to quad in ‘<samp>%rax</samp>’
|
(x86-64 only),
|
|
</li><li> ‘<samp>cqo</samp>’ — sign-extend quad in ‘<samp>%rax</samp>’ to octuple in
|
‘<samp>%rdx:%rax</samp>’ (x86-64 only),
|
</li></ul>
|
|
<p>are called ‘<samp>cbtw</samp>’, ‘<samp>cwtl</samp>’, ‘<samp>cwtd</samp>’, ‘<samp>cltd</samp>’, ‘<samp>cltq</samp>’, and
|
‘<samp>cqto</samp>’ in AT&T naming. <code>as</code> accepts either naming for these
|
instructions.
|
</p>
|
<a name="index-extension-instructions_002c-i386"></a>
|
<a name="index-i386-extension-instructions"></a>
|
<a name="index-extension-instructions_002c-x86_002d64"></a>
|
<a name="index-x86_002d64-extension-instructions"></a>
|
<p>The Intel-syntax extension instructions
|
</p>
|
<ul>
|
<li> ‘<samp>movsx</samp>’ — sign-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg16</samp>’.
|
|
</li><li> ‘<samp>movsx</samp>’ — sign-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg32</samp>’.
|
|
</li><li> ‘<samp>movsx</samp>’ — sign-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg64</samp>’
|
(x86-64 only).
|
|
</li><li> ‘<samp>movsx</samp>’ — sign-extend ‘<samp>reg16/mem16</samp>’ to ‘<samp>reg32</samp>’
|
|
</li><li> ‘<samp>movsx</samp>’ — sign-extend ‘<samp>reg16/mem16</samp>’ to ‘<samp>reg64</samp>’
|
(x86-64 only).
|
|
</li><li> ‘<samp>movsxd</samp>’ — sign-extend ‘<samp>reg32/mem32</samp>’ to ‘<samp>reg64</samp>’
|
(x86-64 only).
|
|
</li><li> ‘<samp>movzx</samp>’ — zero-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg16</samp>’.
|
|
</li><li> ‘<samp>movzx</samp>’ — zero-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg32</samp>’.
|
|
</li><li> ‘<samp>movzx</samp>’ — zero-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg64</samp>’
|
(x86-64 only).
|
|
</li><li> ‘<samp>movzx</samp>’ — zero-extend ‘<samp>reg16/mem16</samp>’ to ‘<samp>reg32</samp>’
|
|
</li><li> ‘<samp>movzx</samp>’ — zero-extend ‘<samp>reg16/mem16</samp>’ to ‘<samp>reg64</samp>’
|
(x86-64 only).
|
</li></ul>
|
|
<p>are called ‘<samp>movsbw/movsxb/movsx</samp>’, ‘<samp>movsbl/movsxb/movsx</samp>’,
|
‘<samp>movsbq/movsb/movsx</samp>’, ‘<samp>movswl/movsxw</samp>’, ‘<samp>movswq/movsxw</samp>’,
|
‘<samp>movslq/movsxl</samp>’, ‘<samp>movzbw/movzxb/movzx</samp>’,
|
‘<samp>movzbl/movzxb/movzx</samp>’, ‘<samp>movzbq/movzxb/movzx</samp>’,
|
‘<samp>movzwl/movzxw</samp>’ and ‘<samp>movzwq/movzxw</samp>’ in AT&T syntax.
|
</p>
|
<a name="index-jump-instructions_002c-i386"></a>
|
<a name="index-call-instructions_002c-i386"></a>
|
<a name="index-jump-instructions_002c-x86_002d64"></a>
|
<a name="index-call-instructions_002c-x86_002d64"></a>
|
<p>Far call/jump instructions are ‘<samp>lcall</samp>’ and ‘<samp>ljmp</samp>’ in
|
AT&T syntax, but are ‘<samp>call far</samp>’ and ‘<samp>jump far</samp>’ in Intel
|
convention.
|
</p>
|
<a name="AT_0026T-Mnemonic-versus-Intel-Mnemonic"></a>
|
<h4 class="subsubsection">9.16.4.2 AT&T Mnemonic versus Intel Mnemonic</h4>
|
|
<a name="index-i386-mnemonic-compatibility"></a>
|
<a name="index-mnemonic-compatibility_002c-i386"></a>
|
|
<p><code>as</code> supports assembly using Intel mnemonic.
|
<code>.intel_mnemonic</code> selects Intel mnemonic with Intel syntax, and
|
<code>.att_mnemonic</code> switches back to the usual AT&T mnemonic with AT&T
|
syntax for compatibility with the output of <code>gcc</code>.
|
Several x87 instructions, ‘<samp>fadd</samp>’, ‘<samp>fdiv</samp>’, ‘<samp>fdivp</samp>’,
|
‘<samp>fdivr</samp>’, ‘<samp>fdivrp</samp>’, ‘<samp>fmul</samp>’, ‘<samp>fsub</samp>’, ‘<samp>fsubp</samp>’,
|
‘<samp>fsubr</samp>’ and ‘<samp>fsubrp</samp>’, are implemented in AT&T System V/386
|
assembler with different mnemonics from those in Intel IA32 specification.
|
<code>gcc</code> generates those instructions with AT&T mnemonic.
|
</p>
|
<ul>
|
<li> ‘<samp>movslq</samp>’ with AT&T mnemonic only accepts 64-bit destination
|
register. ‘<samp>movsxd</samp>’ should be used to encode 16-bit or 32-bit
|
destination register with both AT&T and Intel mnemonics.
|
</li></ul>
|
|
<hr>
|
<div class="header">
|
<p>
|
Next: <a href="i386_002dRegs.html#i386_002dRegs" accesskey="n" rel="next">i386-Regs</a>, Previous: <a href="i386_002dSyntax.html#i386_002dSyntax" accesskey="p" rel="previous">i386-Syntax</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
|
</div>
|
|
|
|
</body>
|
</html>
|
