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<title>Using as: i386-Memory</title>
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<a name="i386_002dMemory"></a>
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<div class="header">
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<p>
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Next: <a href="i386_002dJumps.html#i386_002dJumps" accesskey="n" rel="next">i386-Jumps</a>, Previous: <a href="i386_002dPrefixes.html#i386_002dPrefixes" accesskey="p" rel="previous">i386-Prefixes</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
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<a name="Memory-References"></a>
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<h4 class="subsection">9.16.7 Memory References</h4>
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<a name="index-i386-memory-references"></a>
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<a name="index-memory-references_002c-i386"></a>
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<a name="index-x86_002d64-memory-references"></a>
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<a name="index-memory-references_002c-x86_002d64"></a>
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<p>An Intel syntax indirect memory reference of the form
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</p>
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<div class="smallexample">
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<pre class="smallexample"><var>section</var>:[<var>base</var> + <var>index</var>*<var>scale</var> + <var>disp</var>]
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</pre></div>
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<p>is translated into the AT&T syntax
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</p>
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<div class="smallexample">
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<pre class="smallexample"><var>section</var>:<var>disp</var>(<var>base</var>, <var>index</var>, <var>scale</var>)
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</pre></div>
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<p>where <var>base</var> and <var>index</var> are the optional 32-bit base and
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index registers, <var>disp</var> is the optional displacement, and
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<var>scale</var>, taking the values 1, 2, 4, and 8, multiplies <var>index</var>
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to calculate the address of the operand. If no <var>scale</var> is
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specified, <var>scale</var> is taken to be 1. <var>section</var> specifies the
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optional section register for the memory operand, and may override the
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default section register (see a 80386 manual for section register
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defaults). Note that section overrides in AT&T syntax <em>must</em>
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be preceded by a ‘<samp>%</samp>’. If you specify a section override which
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coincides with the default section register, <code>as</code> does <em>not</em>
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output any section register override prefixes to assemble the given
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instruction. Thus, section overrides can be specified to emphasize which
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section register is used for a given memory operand.
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</p>
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<p>Here are some examples of Intel and AT&T style memory references:
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</p>
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<dl compact="compact">
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<dt>AT&T: ‘<samp>-4(%ebp)</samp>’, Intel: ‘<samp>[ebp - 4]</samp>’</dt>
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<dd><p><var>base</var> is ‘<samp>%ebp</samp>’; <var>disp</var> is ‘<samp>-4</samp>’. <var>section</var> is
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missing, and the default section is used (‘<samp>%ss</samp>’ for addressing with
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‘<samp>%ebp</samp>’ as the base register). <var>index</var>, <var>scale</var> are both missing.
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</p>
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</dd>
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<dt>AT&T: ‘<samp>foo(,%eax,4)</samp>’, Intel: ‘<samp>[foo + eax*4]</samp>’</dt>
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<dd><p><var>index</var> is ‘<samp>%eax</samp>’ (scaled by a <var>scale</var> 4); <var>disp</var> is
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‘<samp>foo</samp>’. All other fields are missing. The section register here
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defaults to ‘<samp>%ds</samp>’.
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</p>
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</dd>
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<dt>AT&T: ‘<samp>foo(,1)</samp>’; Intel ‘<samp>[foo]</samp>’</dt>
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<dd><p>This uses the value pointed to by ‘<samp>foo</samp>’ as a memory operand.
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Note that <var>base</var> and <var>index</var> are both missing, but there is only
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<em>one</em> ‘<samp>,</samp>’. This is a syntactic exception.
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</p>
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</dd>
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<dt>AT&T: ‘<samp>%gs:foo</samp>’; Intel ‘<samp>gs:foo</samp>’</dt>
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<dd><p>This selects the contents of the variable ‘<samp>foo</samp>’ with section
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register <var>section</var> being ‘<samp>%gs</samp>’.
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</p></dd>
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</dl>
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<p>Absolute (as opposed to PC relative) call and jump operands must be
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prefixed with ‘<samp>*</samp>’. If no ‘<samp>*</samp>’ is specified, <code>as</code>
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always chooses PC relative addressing for jump/call labels.
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</p>
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<p>Any instruction that has a memory operand, but no register operand,
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<em>must</em> specify its size (byte, word, long, or quadruple) with an
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instruction mnemonic suffix (‘<samp>b</samp>’, ‘<samp>w</samp>’, ‘<samp>l</samp>’ or ‘<samp>q</samp>’,
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respectively).
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</p>
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<p>The x86-64 architecture adds an RIP (instruction pointer relative)
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addressing. This addressing mode is specified by using ‘<samp>rip</samp>’ as a
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base register. Only constant offsets are valid. For example:
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</p>
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<dl compact="compact">
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<dt>AT&T: ‘<samp>1234(%rip)</samp>’, Intel: ‘<samp>[rip + 1234]</samp>’</dt>
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<dd><p>Points to the address 1234 bytes past the end of the current
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instruction.
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</p>
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</dd>
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<dt>AT&T: ‘<samp>symbol(%rip)</samp>’, Intel: ‘<samp>[rip + symbol]</samp>’</dt>
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<dd><p>Points to the <code>symbol</code> in RIP relative way, this is shorter than
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the default absolute addressing.
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</p></dd>
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</dl>
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<p>Other addressing modes remain unchanged in x86-64 architecture, except
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registers used are 64-bit instead of 32-bit.
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</p>
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<hr>
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<div class="header">
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<p>
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Next: <a href="i386_002dJumps.html#i386_002dJumps" accesskey="n" rel="next">i386-Jumps</a>, Previous: <a href="i386_002dPrefixes.html#i386_002dPrefixes" accesskey="p" rel="previous">i386-Prefixes</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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