<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
|
<html>
|
<!-- This file documents the GNU Assembler "as".
|
|
Copyright (C) 1991-2021 Free Software Foundation, Inc.
|
|
Permission is granted to copy, distribute and/or modify this document
|
under the terms of the GNU Free Documentation License, Version 1.3
|
or any later version published by the Free Software Foundation;
|
with no Invariant Sections, with no Front-Cover Texts, and with no
|
Back-Cover Texts. A copy of the license is included in the
|
section entitled "GNU Free Documentation License".
|
-->
|
<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ -->
|
<head>
|
<title>Using as: RISC-V-Formats</title>
|
|
<meta name="description" content="Using as: RISC-V-Formats">
|
<meta name="keywords" content="Using as: RISC-V-Formats">
|
<meta name="resource-type" content="document">
|
<meta name="distribution" content="global">
|
<meta name="Generator" content="makeinfo">
|
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
|
<link href="index.html#Top" rel="start" title="Top">
|
<link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
|
<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
|
<link href="RISC_002dV_002dDependent.html#RISC_002dV_002dDependent" rel="up" title="RISC-V-Dependent">
|
<link href="RISC_002dV_002dATTRIBUTE.html#RISC_002dV_002dATTRIBUTE" rel="next" title="RISC-V-ATTRIBUTE">
|
<link href="RISC_002dV_002dModifiers.html#RISC_002dV_002dModifiers" rel="previous" title="RISC-V-Modifiers">
|
<style type="text/css">
|
<!--
|
a.summary-letter {text-decoration: none}
|
blockquote.smallquotation {font-size: smaller}
|
div.display {margin-left: 3.2em}
|
div.example {margin-left: 3.2em}
|
div.indentedblock {margin-left: 3.2em}
|
div.lisp {margin-left: 3.2em}
|
div.smalldisplay {margin-left: 3.2em}
|
div.smallexample {margin-left: 3.2em}
|
div.smallindentedblock {margin-left: 3.2em; font-size: smaller}
|
div.smalllisp {margin-left: 3.2em}
|
kbd {font-style:oblique}
|
pre.display {font-family: inherit}
|
pre.format {font-family: inherit}
|
pre.menu-comment {font-family: serif}
|
pre.menu-preformatted {font-family: serif}
|
pre.smalldisplay {font-family: inherit; font-size: smaller}
|
pre.smallexample {font-size: smaller}
|
pre.smallformat {font-family: inherit; font-size: smaller}
|
pre.smalllisp {font-size: smaller}
|
span.nocodebreak {white-space:nowrap}
|
span.nolinebreak {white-space:nowrap}
|
span.roman {font-family:serif; font-weight:normal}
|
span.sansserif {font-family:sans-serif; font-weight:normal}
|
ul.no-bullet {list-style: none}
|
-->
|
</style>
|
|
|
</head>
|
|
<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
|
<a name="RISC_002dV_002dFormats"></a>
|
<div class="header">
|
<p>
|
Next: <a href="RISC_002dV_002dATTRIBUTE.html#RISC_002dV_002dATTRIBUTE" accesskey="n" rel="next">RISC-V-ATTRIBUTE</a>, Previous: <a href="RISC_002dV_002dModifiers.html#RISC_002dV_002dModifiers" accesskey="p" rel="previous">RISC-V-Modifiers</a>, Up: <a href="RISC_002dV_002dDependent.html#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
|
</div>
|
<hr>
|
<a name="RISC_002dV-Instruction-Formats"></a>
|
<h4 class="subsection">9.38.4 RISC-V Instruction Formats</h4>
|
<a name="index-instruction-formats_002c-risc_002dv"></a>
|
<a name="index-RISC_002dV-instruction-formats"></a>
|
|
<p>The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12
|
instruction formats where some of the formats have multiple variants.
|
For the ‘<samp>.insn</samp>’ pseudo directive the assembler recognizes some
|
of the formats.
|
Typically, the most general variant of the instruction format is used
|
by the ‘<samp>.insn</samp>’ directive.
|
</p>
|
<p>The following table lists the abbreviations used in the table of
|
instruction formats:
|
</p>
|
<div class="display">
|
<table>
|
<tr><td width="15%"><pre class="display">opcode</pre></td><td width="40%"><pre class="display">Unsigned immediate or opcode name for 7-bits opcode.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">opcode2</pre></td><td width="40%"><pre class="display">Unsigned immediate or opcode name for 2-bits opcode.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">func7</pre></td><td width="40%"><pre class="display">Unsigned immediate for 7-bits function code.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">func6</pre></td><td width="40%"><pre class="display">Unsigned immediate for 6-bits function code.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">func4</pre></td><td width="40%"><pre class="display">Unsigned immediate for 4-bits function code.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">func3</pre></td><td width="40%"><pre class="display">Unsigned immediate for 3-bits function code.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">func2</pre></td><td width="40%"><pre class="display">Unsigned immediate for 2-bits function code.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">rd</pre></td><td width="40%"><pre class="display">Destination register number for operand x, can be GPR or FPR.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">rd’</pre></td><td width="40%"><pre class="display">Destination register number for operand x,
|
only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">rs1</pre></td><td width="40%"><pre class="display">First source register number for operand x, can be GPR or FPR.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">rs1’</pre></td><td width="40%"><pre class="display">First source register number for operand x,
|
only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">rs2</pre></td><td width="40%"><pre class="display">Second source register number for operand x, can be GPR or FPR.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">rs2’</pre></td><td width="40%"><pre class="display">Second source register number for operand x,
|
only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">simm12</pre></td><td width="40%"><pre class="display">Sign-extended 12-bit immediate for operand x.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">simm20</pre></td><td width="40%"><pre class="display">Sign-extended 20-bit immediate for operand x.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">simm6</pre></td><td width="40%"><pre class="display">Sign-extended 6-bit immediate for operand x.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">uimm8</pre></td><td width="40%"><pre class="display">Unsigned 8-bit immediate for operand x.</pre></td></tr>
|
<tr><td width="15%"><pre class="display">symbol</pre></td><td width="40%"><pre class="display">Symbol or lable reference for operand x.</pre></td></tr>
|
</table>
|
</div>
|
|
<p>The following table lists all available opcode name:
|
</p>
|
<dl compact="compact">
|
<dt><code>C0</code></dt>
|
<dt><code>C1</code></dt>
|
<dt><code>C2</code></dt>
|
<dd><p>Opcode space for compressed instructions.
|
</p>
|
</dd>
|
<dt><code>LOAD</code></dt>
|
<dd><p>Opcode space for load instructions.
|
</p>
|
</dd>
|
<dt><code>LOAD_FP</code></dt>
|
<dd><p>Opcode space for floating-point load instructions.
|
</p>
|
</dd>
|
<dt><code>STORE</code></dt>
|
<dd><p>Opcode space for store instructions.
|
</p>
|
</dd>
|
<dt><code>STORE_FP</code></dt>
|
<dd><p>Opcode space for floating-point store instructions.
|
</p>
|
</dd>
|
<dt><code>AUIPC</code></dt>
|
<dd><p>Opcode space for auipc instruction.
|
</p>
|
</dd>
|
<dt><code>LUI</code></dt>
|
<dd><p>Opcode space for lui instruction.
|
</p>
|
</dd>
|
<dt><code>BRANCH</code></dt>
|
<dd><p>Opcode space for branch instructions.
|
</p>
|
</dd>
|
<dt><code>JAL</code></dt>
|
<dd><p>Opcode space for jal instruction.
|
</p>
|
</dd>
|
<dt><code>JALR</code></dt>
|
<dd><p>Opcode space for jalr instruction.
|
</p>
|
</dd>
|
<dt><code>OP</code></dt>
|
<dd><p>Opcode space for ALU instructions.
|
</p>
|
</dd>
|
<dt><code>OP_32</code></dt>
|
<dd><p>Opcode space for 32-bits ALU instructions.
|
</p>
|
</dd>
|
<dt><code>OP_IMM</code></dt>
|
<dd><p>Opcode space for ALU with immediate instructions.
|
</p>
|
</dd>
|
<dt><code>OP_IMM_32</code></dt>
|
<dd><p>Opcode space for 32-bits ALU with immediate instructions.
|
</p>
|
</dd>
|
<dt><code>OP_FP</code></dt>
|
<dd><p>Opcode space for floating-point operation instructions.
|
</p>
|
</dd>
|
<dt><code>MADD</code></dt>
|
<dd><p>Opcode space for madd instruction.
|
</p>
|
</dd>
|
<dt><code>MSUB</code></dt>
|
<dd><p>Opcode space for msub instruction.
|
</p>
|
</dd>
|
<dt><code>NMADD</code></dt>
|
<dd><p>Opcode space for nmadd instruction.
|
</p>
|
</dd>
|
<dt><code>NMSUB</code></dt>
|
<dd><p>Opcode space for msub instruction.
|
</p>
|
</dd>
|
<dt><code>AMO</code></dt>
|
<dd><p>Opcode space for atomic memory operation instructions.
|
</p>
|
</dd>
|
<dt><code>MISC_MEM</code></dt>
|
<dd><p>Opcode space for misc instructions.
|
</p>
|
</dd>
|
<dt><code>SYSTEM</code></dt>
|
<dd><p>Opcode space for system instructions.
|
</p>
|
</dd>
|
<dt><code>CUSTOM_0</code></dt>
|
<dt><code>CUSTOM_1</code></dt>
|
<dt><code>CUSTOM_2</code></dt>
|
<dt><code>CUSTOM_3</code></dt>
|
<dd><p>Opcode space for customize instructions.
|
</p>
|
</dd>
|
</dl>
|
|
<p>An instruction is two or four bytes in length and must be aligned
|
on a 2 byte boundary. The first two bits of the instruction specify the
|
length of the instruction, 00, 01 and 10 indicates a two byte instruction,
|
11 indicates a four byte instruction.
|
</p>
|
<p>The following table lists the RISC-V instruction formats that are available
|
with the ‘<samp>.insn</samp>’ pseudo directive:
|
</p>
|
<dl compact="compact">
|
<dt><code>R type: .insn r opcode, func3, func7, rd, rs1, rs2</code></dt>
|
<dd><pre class="verbatim">+-------+-----+-----+-------+----+-------------+
|
| func7 | rs2 | rs1 | func3 | rd | opcode |
|
+-------+-----+-----+-------+----+-------------+
|
31 25 20 15 12 7 0
|
</pre>
|
</dd>
|
<dt><code>R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3</code></dt>
|
<dt><code>R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3</code></dt>
|
<dd><pre class="verbatim">+-----+-------+-----+-----+-------+----+-------------+
|
| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode |
|
+-----+-------+-----+-----+-------+----+-------------+
|
31 27 25 20 15 12 7 0
|
</pre>
|
</dd>
|
<dt><code>I type: .insn i opcode, func3, rd, rs1, simm12</code></dt>
|
<dt><code>I type: .insn i opcode, func3, rd, simm12(rs1)</code></dt>
|
<dd><pre class="verbatim">+-------------+-----+-------+----+-------------+
|
| simm12 | rs1 | func3 | rd | opcode |
|
+-------------+-----+-------+----+-------------+
|
31 20 15 12 7 0
|
</pre>
|
</dd>
|
<dt><code>S type: .insn s opcode, func3, rs2, simm12(rs1)</code></dt>
|
<dd><pre class="verbatim">+--------------+-----+-----+-------+-------------+-------------+
|
| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode |
|
+--------------+-----+-----+-------+-------------+-------------+
|
31 25 20 15 12 7 0
|
</pre>
|
</dd>
|
<dt><code>B type: .insn s opcode, func3, rs1, rs2, symbol</code></dt>
|
<dt><code>SB type: .insn sb opcode, func3, rs1, rs2, symbol</code></dt>
|
<dd><pre class="verbatim">+------------+--------------+-----+-----+-------+-------------+-------------+--------+
|
| simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
|
+------------+--------------+-----+-----+-------+-------------+-------------+--------+
|
31 30 25 20 15 12 7 0
|
</pre>
|
</dd>
|
<dt><code>U type: .insn u opcode, rd, simm20</code></dt>
|
<dd><pre class="verbatim">+---------------------------+----+-------------+
|
| simm20 | rd | opcode |
|
+---------------------------+----+-------------+
|
31 12 7 0
|
</pre>
|
</dd>
|
<dt><code>J type: .insn j opcode, rd, symbol</code></dt>
|
<dt><code>UJ type: .insn uj opcode, rd, symbol</code></dt>
|
<dd><pre class="verbatim">+------------+--------------+------------+---------------+----+-------------+
|
| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode |
|
+------------+--------------+------------+---------------+----+-------------+
|
31 30 21 20 12 7 0
|
</pre>
|
</dd>
|
<dt><code>CR type: .insn cr opcode2, func4, rd, rs2</code></dt>
|
<dd><pre class="verbatim">+---------+--------+-----+---------+
|
| func4 | rd/rs1 | rs2 | opcode2 |
|
+---------+--------+-----+---------+
|
15 12 7 2 0
|
</pre>
|
</dd>
|
<dt><code>CI type: .insn ci opcode2, func3, rd, simm6</code></dt>
|
<dd><pre class="verbatim">+---------+-----+--------+-----+---------+
|
| func3 | imm | rd/rs1 | imm | opcode2 |
|
+---------+-----+--------+-----+---------+
|
15 13 12 7 2 0
|
</pre>
|
</dd>
|
<dt><code>CIW type: .insn ciw opcode2, func3, rd, uimm8</code></dt>
|
<dd><pre class="verbatim">+---------+--------------+-----+---------+
|
| func3 | imm | rd' | opcode2 |
|
+---------+--------------+-----+---------+
|
15 13 7 2 0
|
</pre>
|
</dd>
|
<dt><code>CA type: .insn ca opcode2, func6, func2, rd, rs2</code></dt>
|
<dd><pre class="verbatim">+---------+----------+-------+------+--------+
|
| func6 | rd'/rs1' | func2 | rs2' | opcode |
|
+---------+----------+-------+------+--------+
|
15 10 7 5 2 0
|
</pre>
|
</dd>
|
<dt><code>CB type: .insn cb opcode2, func3, rs1, symbol</code></dt>
|
<dd><pre class="verbatim">+---------+--------+------+--------+---------+
|
| func3 | offset | rs1' | offset | opcode2 |
|
+---------+--------+------+--------+---------+
|
15 13 10 7 2 0
|
</pre>
|
</dd>
|
<dt><code>CJ type: .insn cj opcode2, symbol</code></dt>
|
<dd><pre class="verbatim">+---------+--------------------+---------+
|
| func3 | jump target | opcode2 |
|
+---------+--------------------+---------+
|
15 13 7 2 0
|
</pre>
|
|
</dd>
|
</dl>
|
|
<p>For the complete list of all instruction format variants see
|
The RISC-V Instruction Set Manual Volume I: User-Level ISA.
|
</p>
|
<hr>
|
<div class="header">
|
<p>
|
Next: <a href="RISC_002dV_002dATTRIBUTE.html#RISC_002dV_002dATTRIBUTE" accesskey="n" rel="next">RISC-V-ATTRIBUTE</a>, Previous: <a href="RISC_002dV_002dModifiers.html#RISC_002dV_002dModifiers" accesskey="p" rel="previous">RISC-V-Modifiers</a>, Up: <a href="RISC_002dV_002dDependent.html#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
|
</div>
|
|
|
|
</body>
|
</html>
|
