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<title>Using as: AVR Pseudo Instructions</title>
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<a name="AVR-Pseudo-Instructions"></a>
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<div class="header">
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<p>
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Previous: <a href="AVR-Opcodes.html#AVR-Opcodes" accesskey="p" rel="previous">AVR Opcodes</a>, Up: <a href="AVR_002dDependent.html#AVR_002dDependent" accesskey="u" rel="up">AVR-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
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<a name="Pseudo-Instructions"></a>
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<h4 class="subsection">9.5.4 Pseudo Instructions</h4>
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<p>The only available pseudo-instruction <code>__gcc_isr</code> can be activated by
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option <samp>-mgcc-isr</samp>.
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</p>
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<dl compact="compact">
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<dt><code>__gcc_isr 1</code></dt>
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<dd><p>Emit code chunk to be used in avr-gcc ISR prologue.
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It will expand to at most six 1-word instructions, all optional:
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push of <code>tmp_reg</code>, push of <code>SREG</code>,
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push and clear of <code>zero_reg</code>, push of <var>Reg</var>.
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</p>
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</dd>
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<dt><code>__gcc_isr 2</code></dt>
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<dd><p>Emit code chunk to be used in an avr-gcc ISR epilogue.
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It will expand to at most five 1-word instructions, all optional:
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pop of <var>Reg</var>, pop of <code>zero_reg</code>,
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pop of <code>SREG</code>, pop of <code>tmp_reg</code>.
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</p>
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</dd>
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<dt><code>__gcc_isr 0, <var>Reg</var></code></dt>
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<dd><p>Finish avr-gcc ISR function. Scan code since the last prologue
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for usage of: <code>SREG</code>, <code>tmp_reg</code>, <code>zero_reg</code>.
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Prologue chunk and epilogue chunks will be replaced by appropriate code
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to save / restore <code>SREG</code>, <code>tmp_reg</code>, <code>zero_reg</code> and <var>Reg</var>.
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</p>
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</dd>
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</dl>
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<p>Example input:
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</p>
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<div class="example">
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<pre class="example">__vector1:
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__gcc_isr 1
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lds r24, var
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inc r24
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sts var, r24
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__gcc_isr 2
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reti
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__gcc_isr 0, r24
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</pre></div>
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<p>Example output:
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</p>
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<div class="example">
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<pre class="example">00000000 <__vector1>:
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0: 8f 93 push r24
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2: 8f b7 in r24, 0x3f
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4: 8f 93 push r24
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6: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <var>
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a: 83 95 inc r24
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c: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <var>
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10: 8f 91 pop r24
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12: 8f bf out 0x3f, r24
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14: 8f 91 pop r24
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16: 18 95 reti
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</pre></div>
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