/*
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* Copyright (C) 2016-2018 Spreadtrum Communications Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __PCIE_DRV_H__
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#define __PCIE_DRV_H__
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#include <linux/pci.h>
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#define DRVER_NAME "wcn_pcie"
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/* Synopsis PCIE configuration registers */
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/* For Region control 2 */
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#define REGION_EN BIT(31)
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/*
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* 0: Address Match Mode. The iATU operates using addresses as in the outbound
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* direction. The Region Base and Limit Registers must be setup.
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*
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* 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant.
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* Not used for RC.
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*/
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#define MATCH_MODE BIT(30)
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#define ADDR_MATCH_MODE ~BIT(30)
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#define BAR_MATCH_MODE BIT(30)
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#define BAR_NUM (BIT(10) | BIT(9) | BIT(8))
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#define BAR_0 BIT(8)
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#define BAR_1 BIT(9)
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#define BAR_2 (BIT(9) | BIT(8))
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#define IATU_OFFSET_ADDR 0x10000
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#define OBREG0_OFFSET_ADDR (0x10000 + (0 * 0x200))
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#define IBREG0_OFFSET_ADDR (0x10000 + (0 * 0x200) + 0x100)
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#define OBREG1_OFFSET_ADDR (0x10000 + (1 * 0x200))
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#define IBREG1_OFFSET_ADDR (0x10000 + (1 * 0x200) + 0x100)
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struct bar_info {
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resource_size_t mmio_start;
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resource_size_t mmio_end;
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resource_size_t mmio_len;
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unsigned long mmio_flags;
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unsigned char *mem;
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unsigned char *vmem;
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};
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struct dma_buf {
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unsigned long vir;
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unsigned long phy;
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int size;
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};
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struct wcn_pcie_info {
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struct pci_dev *dev;
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struct pci_saved_state *saved_state;
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int legacy_en;
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int msi_en;
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int msix_en;
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int in_use;
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int irq;
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int irq_num;
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int irq_en;
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int bar_num;
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struct bar_info bar[8];
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struct msix_entry msix[100];
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/* board info */
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unsigned char revision;
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unsigned char irq_pin;
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unsigned char irq_line;
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unsigned short sub_vendor_id;
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unsigned short sub_system_id;
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unsigned short vendor_id;
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unsigned short device_id;
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struct char_drv_info *p_char;
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};
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struct inbound_reg {
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unsigned int type;/* region contril 1 ;0:mem, 2:i/o 4:cfg */
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unsigned int en;/* region contril 2 [10:8]:BAR_NUM, */
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unsigned int lower_base_addr;
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unsigned int upper_base_addr;
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unsigned int limit;
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unsigned int lower_target_addr;
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unsigned int upper_target_addr;
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} __packed;
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struct outbound_reg {
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unsigned int type;
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unsigned int en;
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unsigned int lower_base_addr;
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unsigned int upper_base_addr;
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unsigned int limit;
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unsigned int lower_target_addr;
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unsigned int upper_target_addr;
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} __packed;
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int pcie_bar_write(struct wcn_pcie_info *priv, int bar, int offset, char *buf,
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int len);
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int pcie_bar_read(struct wcn_pcie_info *priv, int bar, int offset, char *buf,
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int len);
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char *pcie_bar_vmem(struct wcn_pcie_info *priv, int bar);
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int dmalloc(struct wcn_pcie_info *priv, struct dma_buf *dm, int size);
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int dmfree(struct wcn_pcie_info *priv, struct dma_buf *dm);
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unsigned char *ibreg_base(struct wcn_pcie_info *priv, char region);
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unsigned char *obreg_base(struct wcn_pcie_info *priv, char region);
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int pcie_config_read(struct wcn_pcie_info *priv, int offset, char *buf,
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int len);
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int sprd_pcie_bar_map(struct wcn_pcie_info *priv, int bar, unsigned int addr);
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struct wcn_pcie_info *get_wcn_device_info(void);
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#endif
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