/*
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* Copyright (C) 2016-2018 Spreadtrum Communications Inc.
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <wcn_bus.h>
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#include "edma_engine.h"
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#include "ioctl.h"
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#include "mchn.h"
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#include "pcie.h"
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#include "pcie_dbg.h"
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#include "wcn_log.h"
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#include "wcn_misc.h"
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#include "wcn_op.h"
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#include "wcn_procfs.h"
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static struct wcn_pcie_info *g_pcie_dev;
|
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struct wcn_pcie_info *get_wcn_device_info(void)
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{
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return g_pcie_dev;
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}
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static int sprd_pcie_msi_irq(int irq, void *arg)
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{
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struct wcn_pcie_info *priv = arg;
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/*
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* priv->irq : the first msi irq
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* irq: the current irq
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*/
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irq -= priv->irq;
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msi_irq_handle(irq);
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return IRQ_HANDLED;
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}
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static int sprd_pcie_legacy_irq(int irq, void *arg)
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{
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legacy_irq_handle(irq);
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return IRQ_HANDLED;
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}
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int pcie_bar_write(struct wcn_pcie_info *priv, int bar, int offset,
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char *buf, int len)
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{
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char *mem = priv->bar[bar].vmem;
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mem += offset;
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PCIE_INFO("%s(%d, 0x%x, 0x%x)\n", __func__, bar, offset, *((int *)buf));
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memcpy(mem, buf, len);
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hexdump("read", mem, 16);
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return 0;
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}
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EXPORT_SYMBOL(pcie_bar_write);
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int pcie_bar_read(struct wcn_pcie_info *priv, int bar, int offset,
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char *buf, int len)
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{
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char *mem = priv->bar[bar].vmem;
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mem += offset;
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memcpy(buf, mem, len);
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return 0;
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}
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EXPORT_SYMBOL(pcie_bar_read);
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char *pcie_bar_vmem(struct wcn_pcie_info *priv, int bar)
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{
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if (!priv) {
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PCIE_ERR("sprd pcie_dev NULL\n");
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return NULL;
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}
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return priv->bar[bar].vmem;
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}
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int dmalloc(struct wcn_pcie_info *priv, struct dma_buf *dm, int size)
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{
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struct device *dev = &(priv->dev->dev);
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if (!dev) {
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PCIE_ERR("%s(NULL)\n", __func__);
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return ERROR;
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}
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if (dma_set_mask(dev, DMA_BIT_MASK(64))) {
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PCIE_INFO("dma_set_mask err\n");
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if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64))) {
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PCIE_ERR("dma_set_coherent_mask err\n");
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return ERROR;
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}
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}
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dm->vir =
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(unsigned long)dma_alloc_coherent(dev, size,
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(dma_addr_t *)(&(dm->phy)),
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GFP_DMA);
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if (dm->vir == 0) {
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PCIE_ERR("dma_alloc_coherent err\n");
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return ERROR;
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}
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dm->size = size;
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memset((unsigned char *)(dm->vir), 0x56, size);
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PCIE_INFO("dma_alloc_coherent(%d) 0x%lx 0x%lx\n",
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size, dm->vir, dm->phy);
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return 0;
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}
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EXPORT_SYMBOL(dmalloc);
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int dmfree(struct wcn_pcie_info *priv, struct dma_buf *dm)
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{
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struct device *dev = &(priv->dev->dev);
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if (!dev) {
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PCIE_ERR("%s(NULL)\n", __func__);
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return ERROR;
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}
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PCIE_INFO("dma_free_coherent(%d,0x%lx,0x%lx)\n",
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dm->size, dm->vir, dm->phy);
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dma_free_coherent(dev, dm->size, (void *)(dm->vir), dm->phy);
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memset(dm, 0x00, sizeof(struct dma_buf));
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return ERROR;
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}
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unsigned char *ibreg_base(struct wcn_pcie_info *priv, char region)
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{
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unsigned char *p = pcie_bar_vmem(priv, 4);
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if (!p)
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return NULL;
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if (region > 8)
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return NULL;
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PCIE_INFO("%s(%d):0x%x\n", __func__, region, (0x10100 | (region << 9)));
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/*
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* 0x10000: iATU relative offset to BAR4.
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* BAR4 included map iatu reg information.
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* i= region
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* Base = 0x10000
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* outbound = Base + i * 0x200
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* inbound = Base + i * 0x200 + 0x100
|
*/
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p = p + (0x10100 | (region << 9));
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PCIE_INFO("base =0x%p\n", p);
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return p;
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}
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unsigned char *obreg_base(struct wcn_pcie_info *priv, char region)
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{
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unsigned char *p = pcie_bar_vmem(priv, 4);
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if (!p)
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return NULL;
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if (region > 8)
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return NULL;
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PCIE_INFO("%s(%d):0x%x\n", __func__, region, (0x10000 | (region << 9)));
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p = p + (0x10000 | (region << 9));
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return p;
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}
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static int sprd_ep_addr_map(struct wcn_pcie_info *priv)
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{
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struct inbound_reg *ibreg0;
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struct outbound_reg *obreg0;
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struct outbound_reg *obreg1;
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if (!pcie_bar_vmem(priv, 4)) {
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PCIE_INFO("get bar4 base err\n");
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return -1;
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}
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ibreg0 = (struct inbound_reg *) (pcie_bar_vmem(priv, 4) +
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IBREG0_OFFSET_ADDR);
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obreg0 = (struct outbound_reg *) (pcie_bar_vmem(priv, 4) +
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OBREG0_OFFSET_ADDR);
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obreg1 = (struct outbound_reg *) (pcie_bar_vmem(priv, 4) +
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OBREG1_OFFSET_ADDR);
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ibreg0->lower_target_addr = 0x40000000;
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ibreg0->upper_target_addr = 0x00000000;
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ibreg0->type = 0x00000000;
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ibreg0->limit = 0x00FFFFFF;
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ibreg0->en = REGION_EN | BAR_MATCH_MODE;
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obreg0->type = 0x00000000;
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obreg0->en = REGION_EN & ADDR_MATCH_MODE;
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obreg0->lower_base_addr = 0x00000000;
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obreg0->upper_base_addr = 0x00000080;
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obreg0->limit = 0xffffffff;
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obreg0->lower_target_addr = 0x00000000;
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obreg0->upper_target_addr = 0x00000000;
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obreg1->type = 0x00000000;
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obreg1->en = REGION_EN & ADDR_MATCH_MODE;
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obreg1->lower_base_addr = 0x00000000;
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obreg1->upper_base_addr = 0x00000081;
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obreg1->limit = 0xffffffff;
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obreg1->lower_target_addr = 0x00000000;
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obreg1->upper_target_addr = 0x00000001;
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return 0;
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}
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int pcie_config_read(struct wcn_pcie_info *priv, int offset, char *buf, int len)
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{
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int i, ret;
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for (i = 0; i < len; i++) {
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ret = pci_read_config_byte(priv->dev, i, &(buf[i]));
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if (ret) {
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PCIE_ERR("pci_read_config_dword %d err\n", ret);
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return ERROR;
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}
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}
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return 0;
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}
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int pcie_config_write(struct wcn_pcie_info *priv, int offset,
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char *buf, int len)
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{
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int i, ret;
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for (i = 0; i < len; i++) {
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ret = pci_write_config_byte(priv->dev, i, buf[i]);
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if (ret) {
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PCIE_ERR("%s %d err\n", __func__, ret);
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return ERROR;
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}
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}
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return 0;
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}
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int sprd_pcie_bar_map(struct wcn_pcie_info *priv, int bar, unsigned int addr)
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{
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struct inbound_reg *ibreg = (struct inbound_reg *) ibreg_base(priv,
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bar);
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if (!ibreg) {
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PCIE_ERR("ibreg(%d) NULL\n", bar);
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return -1;
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}
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ibreg->lower_target_addr = addr;
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ibreg->upper_target_addr = 0x00000000;
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ibreg->type = 0x00000000;
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ibreg->limit = 0x00FFFFFF;
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ibreg->en = REGION_EN | BAR_MATCH_MODE;
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PCIE_ERR("%s(%d, 0x%x)\n", __func__, bar, addr);
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return 0;
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}
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EXPORT_SYMBOL(sprd_pcie_bar_map);
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static int sprd_pcie_probe(struct pci_dev *pdev,
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const struct pci_device_id *pci_id)
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{
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struct wcn_pcie_info *priv;
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int ret = -ENODEV, i, flag;
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PCIE_INFO("%s Enter\n", __func__);
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priv = kzalloc(sizeof(struct wcn_pcie_info), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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g_pcie_dev = priv;
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priv->dev = pdev;
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pci_set_drvdata(pdev, priv);
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/* enable device */
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if (pci_enable_device(pdev)) {
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PCIE_ERR("cannot enable device:%s\n", pci_name(pdev));
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goto err_out;
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}
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/* enable bus master capability on device */
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pci_set_master(pdev);
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priv->irq = pdev->irq;
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PCIE_INFO("dev->irq %d\n", pdev->irq);
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priv->legacy_en = 0;
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priv->msi_en = 1;
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priv->msix_en = 0;
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if (priv->legacy_en == 1)
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priv->irq = pdev->irq;
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if (priv->msi_en == 1) {
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priv->irq_num = pci_msi_vec_count(pdev);
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PCIE_INFO("pci_msi_vec_count ret %d\n", priv->irq_num);
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ret = pci_enable_msi_range(pdev, 1, priv->irq_num);
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#if 0
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ret = pci_alloc_irq_vectors(pdev, 1, priv->irq_num,
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PCI_IRQ_MSI);
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#endif
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if (ret > 0) {
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PCIE_INFO("pci_enable_msi_range %d ok\n", ret);
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priv->msi_en = 1;
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} else {
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PCIE_INFO("pci_enable_msi_range err=%d\n", ret);
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priv->msi_en = 0;
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}
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priv->irq = pdev->irq;
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}
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if (priv->msix_en == 1) {
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for (i = 0; i < 65; i++) {
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priv->msix[i].entry = i;
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priv->msix[i].vector = 0;
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}
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priv->irq_num = pci_enable_msix_range(pdev, priv->msix, 1, 64);
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if (priv->irq_num > 0) {
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PCIE_INFO("pci_enable_msix_range %d ok\n",
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priv->irq_num);
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priv->msix_en = 1;
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} else {
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PCIE_INFO("pci_enable_msix_range %d err\n",
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priv->irq_num);
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priv->msix_en = 0;
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}
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priv->irq = pdev->irq;
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}
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PCIE_INFO("dev->irq %d\n", pdev->irq);
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PCIE_INFO("legacy %d msi_en %d, msix_en %d\n", priv->legacy_en,
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priv->msi_en, priv->msix_en);
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for (i = 0; i < 8; i++) {
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flag = pci_resource_flags(pdev, i);
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if (!(flag & IORESOURCE_MEM))
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continue;
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priv->bar[i].mmio_start = pci_resource_start(pdev, i);
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priv->bar[i].mmio_end = pci_resource_end(pdev, i);
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priv->bar[i].mmio_flags = pci_resource_flags(pdev, i);
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priv->bar[i].mmio_len = pci_resource_len(pdev, i);
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priv->bar[i].mem =
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ioremap(priv->bar[i].mmio_start, priv->bar[i].mmio_len);
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priv->bar[i].vmem = priv->bar[i].mem;
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if (priv->bar[i].vmem == NULL) {
|
PCIE_ERR("%s:cannot remap mmio, aborting\n",
|
pci_name(pdev));
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ret = -EIO;
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goto err_out;
|
}
|
PCIE_INFO("BAR(%d) (0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n", i,
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(unsigned long)priv->bar[i].mmio_start,
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(unsigned long)priv->bar[i].mmio_end,
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priv->bar[i].mmio_flags,
|
(unsigned long)priv->bar[i].mmio_len,
|
(unsigned long)priv->bar[i].vmem);
|
}
|
priv->bar_num = 8;
|
ret = pci_request_regions(pdev, DRVER_NAME);
|
if (ret) {
|
priv->in_use = 1;
|
goto err_out;
|
}
|
|
if (priv->legacy_en == 1) {
|
ret = request_irq(priv->irq,
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(irq_handler_t) (&sprd_pcie_legacy_irq),
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IRQF_NO_SUSPEND | IRQF_NO_THREAD | IRQF_PERCPU,
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DRVER_NAME, (void *)priv);
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if (ret)
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PCIE_ERR("%s request_irq(%d), error %d\n", __func__,
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priv->irq, ret);
|
else
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PCIE_INFO("%s request_irq(%d) ok\n", __func__,
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priv->irq);
|
}
|
if (priv->msi_en == 1) {
|
for (i = 0; i < priv->irq_num; i++) {
|
ret =
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request_irq(priv->irq + i,
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(irq_handler_t) (&sprd_pcie_msi_irq),
|
IRQF_SHARED, DRVER_NAME, (void *)priv);
|
if (ret) {
|
PCIE_ERR("%s request_irq(%d), error %d\n",
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__func__, priv->irq + i, ret);
|
break;
|
}
|
PCIE_INFO("%s request_irq(%d) ok\n", __func__,
|
priv->irq + i);
|
}
|
if (i == priv->irq_num)
|
priv->irq_en = 1;
|
}
|
if (priv->msix_en == 1) {
|
for (i = 0; i < priv->irq_num; i++) {
|
ret =
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request_irq(priv->msix[i].vector,
|
(irq_handler_t) (&sprd_pcie_msi_irq),
|
IRQF_SHARED, DRVER_NAME, (void *)priv);
|
if (ret) {
|
PCIE_ERR("%s request_irq(%d), error %d\n",
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__func__, priv->msix[i].vector, ret);
|
break;
|
}
|
|
PCIE_INFO("%s request_irq(%d) ok\n", __func__,
|
priv->msix[i].vector);
|
}
|
}
|
device_wakeup_enable(&(pdev->dev));
|
ret = sprd_ep_addr_map(priv);
|
if (ret < 0)
|
return ret;
|
edma_init(priv);
|
dbg_attach_bus(priv);
|
proc_fs_init();
|
log_dev_init();
|
mdbg_atcmd_owner_init();
|
wcn_op_init();
|
PCIE_INFO("%s ok\n", __func__);
|
|
return 0;
|
|
err_out:
|
kfree(priv);
|
|
return ret;
|
}
|
|
static int sprd_ep_suspend(struct device *dev)
|
{
|
int ret;
|
struct mchn_ops_t *ops;
|
int chn;
|
struct pci_dev *pdev = to_pci_dev(dev);
|
struct wcn_pcie_info *priv = pci_get_drvdata(pdev);
|
|
for (chn = 0; chn < 16; chn++) {
|
ops = mchn_ops(chn);
|
if ((ops != NULL) && (ops->power_notify != NULL)) {
|
ret = ops->power_notify(chn, 0);
|
if (ret != 0) {
|
PCIE_INFO("[%s] chn:%d suspend fail\n",
|
__func__, chn);
|
return ret;
|
}
|
}
|
}
|
|
PCIE_INFO("%s[+]\n", __func__);
|
|
if (!pdev)
|
return 0;
|
|
pci_save_state(to_pci_dev(dev));
|
priv->saved_state = pci_store_saved_state(to_pci_dev(dev));
|
|
ret = pci_enable_wake(pdev, PCI_D3hot, 1);
|
PCIE_INFO("pci_enable_wake(PCI_D3hot) ret %d\n", ret);
|
ret = pci_set_power_state(pdev, PCI_D3hot);
|
PCIE_INFO("pci_set_power_state(PCI_D3hot) ret %d\n", ret);
|
PCIE_INFO("%s[-]\n", __func__);
|
|
return 0;
|
}
|
|
static int sprd_ep_resume(struct device *dev)
|
{
|
int ret;
|
struct mchn_ops_t *ops;
|
int chn;
|
struct pci_dev *pdev = to_pci_dev(dev);
|
struct wcn_pcie_info *priv = pci_get_drvdata(pdev);
|
|
PCIE_INFO("%s[+]\n", __func__);
|
if (!pdev)
|
return 0;
|
|
pci_load_and_free_saved_state(to_pci_dev(dev), &priv->saved_state);
|
pci_restore_state(to_pci_dev(dev));
|
pci_write_config_dword(to_pci_dev(dev), 0x60, 0);
|
|
ret = pci_set_power_state(pdev, PCI_D0);
|
PCIE_INFO("pci_set_power_state(PCI_D0) ret %d\n", ret);
|
ret = pci_enable_wake(pdev, PCI_D0, 0);
|
PCIE_INFO("pci_enable_wake(PCI_D0) ret %d\n", ret);
|
|
usleep_range(50000, 51000);
|
ret = sprd_ep_addr_map(priv);
|
if (ret)
|
return ret;
|
usleep_range(10000, 11000);
|
|
for (chn = 0; chn < 16; chn++) {
|
ops = mchn_ops(chn);
|
if ((ops != NULL) && (ops->power_notify != NULL)) {
|
ret = ops->power_notify(chn, 1);
|
if (ret != 0) {
|
PCIE_INFO("[%s] chn:%d resume fail\n",
|
__func__, chn);
|
return ret;
|
}
|
}
|
}
|
return 0;
|
}
|
|
const struct dev_pm_ops sprd_ep_pm_ops = {
|
SET_SYSTEM_SLEEP_PM_OPS(sprd_ep_suspend, sprd_ep_resume)
|
};
|
|
static void sprd_pcie_remove(struct pci_dev *pdev)
|
{
|
int i;
|
struct wcn_pcie_info *priv;
|
|
priv = (struct wcn_pcie_info *) pci_get_drvdata(pdev);
|
edma_deinit();
|
ioctlcmd_deinit(priv);
|
mpool_free();
|
if (priv->legacy_en == 1)
|
free_irq(priv->irq, (void *)priv);
|
|
if (priv->msi_en == 1) {
|
for (i = 0; i < priv->irq_num; i++)
|
free_irq(priv->irq + i, (void *)priv);
|
|
pci_disable_msi(pdev);
|
}
|
if (priv->msix_en == 1) {
|
PCIE_INFO("disable MSI-X");
|
for (i = 0; i < priv->irq_num; i++)
|
free_irq(priv->msix[i].vector, (void *)priv);
|
|
pci_disable_msix(pdev);
|
}
|
for (i = 0; i < priv->bar_num; i++) {
|
if (priv->bar[i].mem)
|
iounmap(priv->bar[i].mem);
|
}
|
pci_release_regions(pdev);
|
kfree(priv);
|
pci_set_drvdata(pdev, NULL);
|
pci_disable_device(pdev);
|
}
|
|
static struct pci_device_id sprd_pcie_tbl[] = {
|
{0x1db3, 0x2355, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
|
{0,}
|
};
|
|
MODULE_DEVICE_TABLE(pci, sprd_pcie_tbl);
|
static struct pci_driver sprd_pcie_driver = {
|
.name = DRVER_NAME,
|
.id_table = sprd_pcie_tbl,
|
.probe = sprd_pcie_probe,
|
.remove = sprd_pcie_remove,
|
.driver = {
|
.pm = &sprd_ep_pm_ops,
|
},
|
};
|
|
static int __init sprd_pcie_init(void)
|
{
|
int ret = 0;
|
|
PCIE_INFO("%s init\n", __func__);
|
|
ret = pci_register_driver(&sprd_pcie_driver);
|
PCIE_INFO("pci_register_driver ret %d\n", ret);
|
|
return ret;
|
}
|
|
static void __exit sprd_pcie_exit(void)
|
{
|
PCIE_INFO("%s\n", __func__);
|
pci_unregister_driver(&sprd_pcie_driver);
|
}
|
|
module_init(sprd_pcie_init);
|
module_exit(sprd_pcie_exit);
|
|
MODULE_LICENSE("GPL");
|
MODULE_DESCRIPTION("marlin3 pcie/edma drv");
|
