/*
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* Copyright (C) 2018 Spreadtrum Communications Inc.
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __EDMA_ENGIN_H__
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#define __EDMA_ENGIN_H__
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#include "pcie_dbg.h"
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#include "pcie.h"
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enum ISR_TASK_MSG_ID {
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ISR_MSG_NULL = 0,
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ISR_MSG_TX_POP,
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ISR_MSG_TX_COMPLETE,
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ISR_MSG_RX_POP,
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ISR_MSG_RX_PUSH,
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ISR_MSG_INTx,
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ISR_MSG_EXIT_FUNC,
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};
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enum LINK_MODE_TYPE {
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TWO_LINK_MODE = 0,
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ONE_LINK_MODE,
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NON_LINK_MODE,
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};
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enum ADDR_REGION_TYPE {
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CPU64 = 0x0,
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AXI40 = 0x1,
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AHB32 = 0x2,
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};
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#define CONFIG_TASKLET_SUPPORT (1)
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#define INCR_RING_BUFF_INDX(indx, max_num) \
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((((indx) + 1) < (max_num)) ? ((indx) + 1) : (0))
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#define GET_32_OF_40(a) ((unsigned int)((unsigned long) \
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(mpool_vir_to_phy(a)) & 0xFFFFFFFF))
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#define GET_8_OF_40(a) (0x80)
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#define SET_32_OF_40(a, v) do { \
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unsigned long l = (unsigned long)(a); \
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if (sizeof(unsigned long) == sizeof(unsigned int)) { \
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a = (void *)((l&0x00000000)|(v)); \
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} else { \
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a = (void *)((l&0xFFFFFFFF00000000)|(v)); \
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} \
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} while (0)
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#define SET_8_OF_40(a, v) do { \
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unsigned long l = (unsigned long)(a); \
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if (sizeof(unsigned long) != sizeof(unsigned int)) \
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a = (void *)((l&0xFFFFFF00FFFFFFFF) |\
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((unsigned long)(v) << 32));\
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} while (0)
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#define COMPARE_40_BIT(a, b) ((sizeof(unsigned int) == \
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sizeof(unsigned long)) ? \
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(!((unsigned long)(a) ^ (unsigned long)(b))) : \
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(!(((unsigned long)(a) ^ (unsigned long)(b)) & 0xFFFFFFFFFF)))
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struct cpdu_head {
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struct cpdu_head *next;
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unsigned int __next:8;
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unsigned int len:16;
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unsigned int offset:8;
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unsigned int rsvd;
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};
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#ifdef __FOR_THREADX_H__
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#define GET_32_OF_40(a) ((unsigned int)(a))
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#define GET_8_OF_40(a) (0)
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#define SET_32_OF_40(a, v) (a = (struct desc *)(v))
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#define SET_8_OF_40(a, v)
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#define COMPARE_40_BIT(a, b) ((sizeof(unsigned int) == \
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sizeof(unsigned long)) ? \
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(!((unsigned long)(a) ^ (unsigned long)(b))) : \
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(!(((unsigned long)(a) ^ (unsigned long)(b)) & 0xFFFFFFFFFF)))
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struct mbuf_t {
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struct mbuf_t *next;
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unsigned char *buf;
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unsigned short len;
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unsigned short rsvd;
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unsigned int seq;
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};
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#endif
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union dma_glb_pause_reg {
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unsigned int reg;
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struct {
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unsigned int rf_dma_pause:1;
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unsigned int rsvd0:1;
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unsigned int rf_dma_pause_status:1;
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unsigned int rsvd1:5;
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unsigned int rf_dma_dst_outstanding_num:4;
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unsigned int rf_dma_src_outstanding_num:4;
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unsigned int edma_reg_rclk_cg_en:1;
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unsigned int edma_glb_cfg_wclk_cg_en:1;
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unsigned int edma_chn_cfg_wclk_cg_en:1;
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unsigned int edma_req_cid_wclk_cg_en:1;
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unsigned int edma_chn_int_clk_cg_en:1;
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unsigned int edma_axi_clk_cg_en:1;
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unsigned int rsvd2:2;
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unsigned int rf_dma_pcie_legacy_int_en:1;
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unsigned int rsvd3:7;
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} bit;
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};
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union dma_glb_prot_reg {
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unsigned int reg;
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struct {
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unsigned int rf_dma_pause_prot:1;
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unsigned int rf_dma_int_raw_status_prot:1;
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unsigned int rf_dma_int_mask_status_prot:1;
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unsigned int rf_dma_req_status_prot:1;
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unsigned int rf_dma_debug_status_prot:1;
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unsigned int rf_dma_arb_sel_prot:1;
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unsigned int rf_dma_sync_sec_normal_prot:1;
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unsigned int rsvd:25;
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} bit;
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};
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union dma_glb_msix_value_reg {
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unsigned int reg;
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struct {
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unsigned int rf_dma_pcie_msix_value:22;
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unsigned int rsvd:2;
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unsigned int rf_dma_pcie_msix_reg_addr_hi:8;
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} bit;
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};
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union dma_chn_int_reg {
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unsigned int reg;
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struct {
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unsigned int rf_chn_tx_pop_int_en:1;
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unsigned int rf_chn_tx_complete_int_en:1;
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unsigned int rf_chn_rx_pop_int_en:1;
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unsigned int rf_chn_rx_push_int_en:1;
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unsigned int rf_chn_cfg_err_int_en:1;
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unsigned int rsvd0:3;
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unsigned int rf_chn_tx_pop_int_raw_status:1;
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unsigned int rf_chn_tx_complete_int_raw_status:1;
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unsigned int rf_chn_rx_pop_int_raw_status:1;
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unsigned int rf_chn_rx_push_int_raw_status:1;
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unsigned int rf_chn_cfg_err_int_raw_status:1;
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unsigned int rsvd1:3;
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unsigned int rf_chn_tx_pop_int_mask_status:1;
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unsigned int rf_chn_tx_complete_int_mask_status:1;
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unsigned int rf_chn_rx_pop_int_mask_status:1;
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unsigned int rf_chn_rx_push_int_mask_status:1;
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unsigned int rf_chn_cfg_err_int_mask_status:1;
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unsigned int rsvd2:3;
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unsigned int rf_chn_tx_pop_int_clr:1;
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unsigned int rf_chn_tx_complete_int_clr:1;
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unsigned int rf_chn_rx_pop_int_clr:1;
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unsigned int rf_chn_rx_push_int_clr:1;
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unsigned int rf_chn_cfg_err_int_clr:1;
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unsigned int rsvd3:3;
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} bit;
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};
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union dma_chn_tx_req_reg {
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unsigned int reg;
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struct {
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unsigned int rf_chn_tx_req:1;
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unsigned int rsvd:31;
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} bit;
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};
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union dma_chn_rx_req_reg {
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unsigned int reg;
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struct {
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unsigned int rf_chn_rx_req:1;
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unsigned int rsvd:31;
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} bit;
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};
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union dma_chn_cfg_reg {
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unsigned int reg;
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struct {
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unsigned int rf_chn_en:1;
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unsigned int rsvd0:3;
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unsigned int rf_chn_list_mode:2;
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unsigned int rf_chn_int_to_ap_type:1;
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unsigned int rf_chn_dir:1;
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unsigned int rf_chn_swt_mode:2;
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unsigned int rf_chn_priority:2;
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unsigned int rf_dont_wait_ddone:1;
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unsigned int rf_chn_req_mode:1;
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unsigned int rf_chn_int_out_sel:1;
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unsigned int rsvd1:1;
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unsigned int rf_chn_sem_value:8;
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unsigned int rf_chn_err_status:3;
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unsigned int rsvd2:5;
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} bit;
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};
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union dma_dscr_trans_len_reg {
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unsigned int reg;
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struct {
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unsigned int rf_chn_trsc_len:16;
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unsigned int rf_rsvd0:8;
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unsigned int rf_chn_done:1;
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unsigned int rf_chn_pause:1;
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unsigned int rf_chn_tx_intr:1;
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unsigned int rf_chn_rx_intr:1;
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unsigned int rf_chn_eof:1;
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unsigned int rf_rsvd1:3;
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} bit;
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};
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union dma_dscr_ptr_high_reg {
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unsigned int reg;
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struct {
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unsigned int rf_chn_src_data_addr_high:8;
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unsigned int rf_chn_dst_data_addr_high:8;
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unsigned int rf_chn_tx_next_dscr_ptr_high:8;
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unsigned int rf_chn_rx_next_dscr_ptr_high:8;
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} bit;
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};
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union dma_dscr_req1_cid_reg {
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unsigned int reg;
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struct {
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unsigned int rf_chn_req1_cid:6;
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unsigned int rf_rsvd2:26;
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} bit;
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};
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struct edma_glb_reg {
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union dma_glb_pause_reg dma_pause;
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unsigned int dma_int_raw_status;
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unsigned int dma_int_mask_status;
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unsigned int dma_req_status;
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unsigned int dma_debug_status;
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unsigned int dma_arb_sel_status;
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unsigned int dma_chn_arprot;
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unsigned int dma_chn_awprot;
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unsigned int dma_chn_prot_flag;
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union dma_glb_prot_reg dma_glb_prot;
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unsigned int dma_req_cid_prot;
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unsigned int dma_sync_sec_nomal;
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unsigned int dma_pcie_msix_reg_addr_low;
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union dma_glb_msix_value_reg dma_pcie_msix_value;
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};
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struct desc {
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union dma_dscr_trans_len_reg chn_trans_len;
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union dma_dscr_ptr_high_reg chn_ptr_high;
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unsigned int rf_chn_tx_next_dscr_ptr_low;
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unsigned int rf_chn_rx_next_dscr_ptr_low;
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unsigned int rf_chn_data_src_addr_low;
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unsigned int rf_chn_data_dst_addr_low;
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union {
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struct desc *p;
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unsigned int t[2];
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} next;
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union {
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void *p;
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unsigned char *src;
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unsigned int t[2];
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} link;
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union {
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unsigned char *p;
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unsigned char *dst;
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unsigned int t[2];
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} buf;
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};
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struct edma_chn_reg {
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union dma_chn_int_reg dma_int;
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union dma_chn_tx_req_reg dma_tx_req;
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union dma_chn_rx_req_reg dma_rx_req;
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union dma_chn_cfg_reg dma_cfg;
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struct desc dma_dscr;
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};
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enum ERROR_CODE {
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OK = 0,
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ERROR = -1,
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TIMEOUT = -2,
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};
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struct event_t {
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int id;
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int flag;
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struct semaphore wait_sem;
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struct timespec time;
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struct tasklet_struct *tasklet;
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};
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struct lock_sw {
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void *entity;
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unsigned long flag;
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char *name;
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};
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struct irq_lock_t {
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spinlock_t *irq_spinlock_p;
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unsigned long flag;
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char *name;
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};
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struct dscr_ring {
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int size;
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int free;
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struct desc *head;
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struct desc *tail;
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unsigned char *mem;
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struct irq_lock_t lock;
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};
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struct edma_pending_q {
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struct {
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void *head;
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void *tail;
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int num;
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} ring[32];
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int wt;
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int rd;
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int max;
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int status;
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int chn;
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struct irq_lock_t lock;
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};
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struct isr_msg_queue {
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unsigned int seq;
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unsigned short chn;
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unsigned short evt;
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union dma_chn_int_reg dma_int;
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};
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struct msg_q {
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unsigned int seq;
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unsigned int wt;
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unsigned int rd;
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unsigned int max;
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unsigned int size;
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unsigned char *mem;
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struct irq_lock_t lock;
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struct event_t event;
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};
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struct edma_info {
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struct edma_glb_reg *dma_glb_reg;
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struct edma_chn_reg *dma_chn_reg;
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int (*enable)(void);
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int (*reset)(void);
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int ap;
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struct {
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int mode;
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int wait;
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int interval;
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int tx_complete_verify;
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struct event_t event;
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struct dscr_ring dscr_ring;
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unsigned char dir;
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unsigned char inout;
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unsigned char state;
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struct edma_pending_q pending_q;
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} chn_sw[32];
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struct {
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int state;
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void *entity;
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struct msg_q q;
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} isr_func;
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struct wcn_pcie_info *pcie_info;
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};
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int edma_init(struct wcn_pcie_info *pcie_info);
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int edma_deinit(void);
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int edma_chn_init(int chn, int mode, int inout, int max_trans);
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int edma_one_link_dscr_buf_bind(struct desc *dscr, unsigned char *dst,
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unsigned char *src, unsigned short len);
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struct edma_info *edma_info(void);
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int msi_irq_handle(int irq);
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int legacy_irq_handle(int data);
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int edma_push_link(int chn, void *head, void *tail, int num);
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int edma_push_link_async(int chn, void *head, void *tail, int num);
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int edma_push_link_wait_complete(int chn, void *head, void *tail,
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int num, int timeout);
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int mchn_hw_pop_link(int chn, void *head, void *tail, int num);
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int mchn_hw_cb_in_irq(int chn);
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int mchn_hw_max_pending(int chn);
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int edma_tp_count(int chn, void *head, void *tail, int num);
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void *mpool_malloc(int len);
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int mpool_free(void);
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void *pcie_alloc_memory(int len);
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int delete_queue(struct msg_q *q);
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#endif
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