/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __WCN_INTEGRATE_DEV_H__
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#define __WCN_INTEGRATE_DEV_H__
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#include "rf.h"
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/* The name should be set the same as DTS */
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#define WCN_MARLIN_DEV_NAME "wcn_btwf"
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#define WCN_GNSS_DEV_NAME "wcn_gnss"
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/*
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* ASIC: enable or disable vddwifipa and vddcon,
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* the interval time should more than 1ms.
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*/
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#define VDDWIFIPA_VDDCON_MIN_INTERVAL_TIME (10000) /* us */
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#define VDDWIFIPA_VDDCON_MAX_INTERVAL_TIME (30000) /* us */
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enum wcn_marlin_sub_sys {
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WCN_MARLIN_BLUETOOTH = 0,
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WCN_MARLIN_FM,
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WCN_MARLIN_WIFI,
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WCN_MARLIN_MDBG = 6,
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WCN_MARLIN_ALL = 7,
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};
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enum wcn_gnss_sub_sys {
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/*
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* The value is different with wcn_marlin_sub_sys
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* Or the start interface can't distinguish
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* Marlin or GNSS
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*/
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WCN_GNSS = 16,
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WCN_GNSS_BD,
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WCN_GNSS_ALL,
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};
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#define WCN_BTWF_FILENAME "wcnmodem"
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#define WCN_GNSS_FILENAME "gpsgl"
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#define WCN_GNSS_BD_FILENAME "gpsbd"
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/* NOTES:If DTS config more than REG_CTRL_CNT_MAX REGs */
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#define REG_CTRL_CNT_MAX 8
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/* NOTES:If DTS config more than REG_SHUTDOWN_CNT_MAX REGs */
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#define REG_SHUTDOWN_CNT_MAX 4
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#define WCN_INTEGRATE_PLATFORM_DEBUG 0
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#define SUSPEND_RESUME_ENABLE 0
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#define WCN_OPEN_MAX_CNT (0x10)
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/* default VDDCON voltage is 1.6v, work voltage is 1.2v */
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#define WCN_VDDCON_WORK_VOLTAGE (1200000)
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/* default VDDCON voltage is 3.3v, work voltage is 3.0v */
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#define WCN_VDDWIFIPA_WORK_VOLTAGE (3000000)
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#define WCN_PROC_FILE_LENGTH_MAX (63)
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#define FIRMWARE_FILEPATHNAME_LENGTH_MAX 256
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#define WCN_MARLIN_MASK 0xcf /* Base on wcn_marlin_sub_sys */
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#define WCN_MARLIN_BTWIFI_MASK 0x05
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#define WCN_GNSS_MASK (1<<WCN_GNSS)
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#define WCN_GNSS_BD_MASK (1<<WCN_GNSS_BD)
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#define WCN_GNSS_ALL_MASK (WCN_GNSS_MASK|WCN_GNSS_BD_MASK)
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/* type for base REGs */
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enum {
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REGMAP_AON_APB = 0x0, /* AON APB */
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REGMAP_PMU_APB,
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/*
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* NOTES:SharkLE use it,but PIKE2 not.
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* We should config the DTS for PIKE2 also.
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*/
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REGMAP_PUB_APB, /* SharkLE only:for ddr offset */
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REGMAP_ANLG_WRAP_WCN,
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REGMAP_ANLG_PHY_G5, /* SharkL3 only */
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REGMAP_ANLG_PHY_G6, /* SharkLE only */
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REGMAP_WCN_REG, /* SharkL3 only:0x403A 0000 */
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REGMAP_TYPE_NR,
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};
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#if WCN_INTEGRATE_PLATFORM_DEBUG
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enum wcn_integrate_platform_debug_case {
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NORMAL_CASE = 0,
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WCN_START_MARLIN_DEBUG,
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WCN_STOP_MARLIN_DEBUG,
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WCN_START_MARLIN_DDR_FIRMWARE_DEBUG,
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/* Next for GNSS */
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WCN_START_GNSS_DEBUG,
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WCN_STOP_GNSS_DEBUG,
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WCN_START_GNSS_DDR_FIRMWARE_DEBUG,
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/* Print Info */
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WCN_PRINT_INFO,
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WCN_BRINGUP_DEBUG,
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};
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#endif
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struct platform_proc_file_entry {
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char *name;
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struct proc_dir_entry *platform_proc_dir_entry;
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struct wcn_device *wcn_dev;
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unsigned int flag;
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};
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#define MAX_PLATFORM_ENTRY_NUM 0x10
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enum {
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BE_SEGMFG = (0x1 << 4),
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BE_RDONLY = (0x1 << 5),
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BE_WRONLY = (0x1 << 6),
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BE_CPDUMP = (0x1 << 7),
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BE_MNDUMP = (0x1 << 8),
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BE_RDWDT = (0x1 << 9),
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BE_RDWDTS = (0x1 << 10),
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BE_RDLDIF = (0x1 << 11),
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BE_LD = (0x1 << 12),
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BE_CTRL_ON = (0x1 << 13),
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BE_CTRL_OFF = (0x1 << 14),
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};
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enum {
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CP_NORMAL_STATUS = 0,
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CP_STOP_STATUS,
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CP_MAX_STATUS,
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};
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struct wcn_platform_fs {
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struct proc_dir_entry *platform_proc_dir_entry;
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struct platform_proc_file_entry entrys[MAX_PLATFORM_ENTRY_NUM];
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};
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struct wcn_proc_data {
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int (*start)(void *arg);
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int (*stop)(void *arg);
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};
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struct wcn_init_data {
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char *devname;
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phys_addr_t base; /* CP base addr */
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u32 maxsz; /* CP max size */
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int (*start)(void *arg);
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int (*stop)(void *arg);
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int (*suspend)(void *arg);
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int (*resume)(void *arg);
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int type;
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};
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/* CHIP if include GNSS */
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#define WCN_INTERNAL_INCLUD_GNSS_VAL (0)
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#define WCN_INTERNAL_NOINCLUD_GNSS_VAL (0xab520)
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/* WIFI cali */
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#define WIFI_CALIBRATION_FLAG_VALUE (0xefeffefe)
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#define WIFI_CALIBRATION_FLAG_CLEAR_VALUE (0x12345678)
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/*GNSS cali*/
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#define GNSS_CALIBRATION_FLAG_CLEAR_ADDR (0x00150028)
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#define GNSS_CALIBRATION_FLAG_CLEAR_VALUE (0)
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#define GNSS_CALIBRATION_FLAG_CLEAR_ADDR_CP \
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(GNSS_CALIBRATION_FLAG_CLEAR_ADDR + 0x300000)
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#define GNSS_WAIT_CP_INIT_COUNT (256)
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#define GNSS_CALI_DONE_FLAG (0x1314520)
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#define GNSS_WAIT_CP_INIT_POLL_TIME_MS (20) /* 20ms */
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struct wifi_calibration {
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struct wifi_config_t config_data;
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struct wifi_cali_t cali_data;
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};
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/* wifi efuse data, default value comes from PHY team */
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#define WIFI_EFUSE_BLOCK_COUNT (3)
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#define MARLIN_CP_INIT_READY_MAGIC (0xababbaba)
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#define MARLIN_CP_INIT_START_MAGIC (0x5a5a5a5a)
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#define MARLIN_CP_INIT_SUCCESS_MAGIC (0x13579bdf)
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#define MARLIN_CP_INIT_FALIED_MAGIC (0x88888888)
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#define MARLIN_WAIT_CP_INIT_POLL_TIME_MS (20) /* 20ms */
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#define MARLIN_WAIT_CP_INIT_COUNT (256)
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#define MARLIN_WAIT_CP_INIT_MAX_TIME (20000)
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#define WCN_WAIT_SLEEP_MAX_COUNT (32)
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/* begin : for gnss module */
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/* record efuse, GNSS_EFUSE_DATA_OFFSET is defined in gnss.h */
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#define GNSS_EFUSE_BLOCK_COUNT (3)
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#define GNSS_EFUSE_ENABLE_ADDR (0x150024)
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#define GNSS_EFUSE_ENABLE_VALUE (0x20190E0E)
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/* end: for gnss */
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#define WCN_BOOT_CP2_OK 0
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#define WCN_BOOT_CP2_ERR_DONW_IMG 1
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#define WCN_BOOT_CP2_ERR_BOOT 2
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struct wcn_device {
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char *name;
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/* DTS info: */
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/*
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* wcn and gnss ctrl_reg num
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* from ctrl-reg[0] to ctrl-reg[ctrl-probe-num - 1]
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* need init in the driver probe stage
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*/
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u32 ctrl_probe_num;
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u32 ctrl_reg[REG_CTRL_CNT_MAX]; /* offset */
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u32 ctrl_mask[REG_CTRL_CNT_MAX];
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u32 ctrl_value[REG_CTRL_CNT_MAX];
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/*
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* Some REGs Read and Write has about 0x1000 offset;
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* REG_write - REG_read=0x1000, the DTS value is write value
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*/
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u32 ctrl_rw_offset[REG_CTRL_CNT_MAX];
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u32 ctrl_us_delay[REG_CTRL_CNT_MAX];
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u32 ctrl_type[REG_CTRL_CNT_MAX]; /* the value is pmu or apb */
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struct regmap *rmap[REGMAP_TYPE_NR];
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u32 reg_nr;
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/* Shut down group */
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u32 ctrl_shutdown_reg[REG_SHUTDOWN_CNT_MAX];
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u32 ctrl_shutdown_mask[REG_SHUTDOWN_CNT_MAX];
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u32 ctrl_shutdown_value[REG_SHUTDOWN_CNT_MAX];
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u32 ctrl_shutdown_rw_offset[REG_SHUTDOWN_CNT_MAX];
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u32 ctrl_shutdown_us_delay[REG_SHUTDOWN_CNT_MAX];
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u32 ctrl_shutdown_type[REG_SHUTDOWN_CNT_MAX];
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/* struct regmap *rmap_shutdown[REGMAP_TYPE_NR]; */
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u32 reg_shutdown_nr; /* REG_SHUTDOWN_CNT_MAX */
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phys_addr_t base_addr;
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bool download_status;
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char *file_path;
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char *file_path_ext;
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char firmware_path[FIRMWARE_FILEPATHNAME_LENGTH_MAX];
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char firmware_path_ext[FIRMWARE_FILEPATHNAME_LENGTH_MAX];
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u32 file_length;
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/* FS OPS info: */
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struct wcn_platform_fs platform_fs;
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int status;
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u32 wcn_open_status; /* marlin or gnss subsys status */
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u32 boot_cp_status;
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/* driver OPS */
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int (*start)(void *arg);
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int (*stop)(void *arg);
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u32 maxsz;
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struct mutex power_lock;
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u32 power_state;
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struct regulator *vddwifipa;
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struct mutex vddwifipa_lock;
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char *write_buffer;
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struct delayed_work power_wq;
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struct work_struct load_wq;
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struct delayed_work cali_wq;
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struct completion download_done;
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};
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struct wcn_device_manage {
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struct wcn_device *btwf_device;
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struct wcn_device *gnss_device;
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struct regulator *vddwcn;
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struct mutex vddwcn_lock;
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int vddwcn_en_count;
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int gnss_type;
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bool vddcon_voltage_setted;
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bool btwf_calibrated;
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};
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extern struct wcn_device_manage s_wcn_device;
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static inline bool wcn_dev_is_marlin(struct wcn_device *dev)
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{
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return dev == s_wcn_device.btwf_device;
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}
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static inline bool wcn_dev_is_gnss(struct wcn_device *dev)
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{
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return dev == s_wcn_device.gnss_device;
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}
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void wcn_cpu_bootup(struct wcn_device *wcn_dev);
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#endif
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