/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __INC_PHYDM_API_H_8822B__
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#define __INC_PHYDM_API_H_8822B__
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#if (RTL8822B_SUPPORT == 1)
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#define PHY_CONFIG_VERSION_8822B "28.5.34"
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/* @2017.01.18 */
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/* @(HW user guide version: R28, SW user guide version: R05, Modification: R34)*/
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/* @remove A cut setting, refine CCK txfilter and OFDM CCA setting by YuChen*/
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#define SMTANT_TMP_RFE_TYPE 100
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#define ANT_2T3R_RFE_TYPE 101
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#define ANT_2T4R_RFE_TYPE 102
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#define INVALID_RF_DATA 0xffffffff
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#define INVALID_TXAGC_DATA 0xff
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#define PSD_VAL_NUM 3
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#define PSD_SMP_NUM 3
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#define FREQ_PT_2G_NUM 14
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#define FREQ_PT_5G_NUM 10
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#define number_channel_interferecne 4
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#define config_phydm_read_rf_check_8822b(data) (data != INVALID_RF_DATA)
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#define config_phydm_read_txagc_check_8822b(data) (data != INVALID_TXAGC_DATA)
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enum agc_tab_sel {
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DEFAULT_AGC_TABLE,
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LNA_SAT_AGC_TABLE,
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AUTO_AGC_TABLE
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};
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void phydm_rfe_8822b_init(struct dm_struct *dm);
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boolean
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phydm_rfe_8822b(struct dm_struct *dm, u8 channel);
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u32 config_phydm_read_rf_reg_8822b(struct dm_struct *dm,
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enum rf_path path,
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u32 reg_addr, u32 bit_mask);
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boolean
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config_phydm_write_rf_reg_8822b(struct dm_struct *dm,
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enum rf_path path, u32 reg_addr,
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u32 bit_mask, u32 data);
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boolean
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config_phydm_write_txagc_8822b(struct dm_struct *dm, u32 pw_idx,
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enum rf_path path, u8 hw_rate);
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u8 config_phydm_read_txagc_8822b(struct dm_struct *dm,
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enum rf_path path, u8 hw_rate);
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void phydm_dynamic_spur_det_eliminate(struct dm_struct *dm);
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boolean
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config_phydm_switch_band_8822b(struct dm_struct *dm,
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u8 central_ch);
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boolean
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config_phydm_switch_channel_8822b(struct dm_struct *dm,
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u8 central_ch);
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__iram_odm_func__
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boolean
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config_phydm_switch_agc_tab_8822b(struct dm_struct *dm,
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u8 channel, enum agc_tab_sel tab_sel);
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boolean
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config_phydm_switch_bandwidth_8822b(struct dm_struct *dm,
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u8 primary_ch_idx,
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enum channel_width bw);
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boolean
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config_phydm_switch_channel_bw_8822b(struct dm_struct *dm,
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u8 central_ch,
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u8 primary_ch_idx,
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enum channel_width bw);
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void
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phydm_config_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path,
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enum bb_path tx_path_sel_1ss,
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enum bb_path tx_path_sel_cck);
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boolean
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config_phydm_trx_mode_8822b(struct dm_struct *dm,
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enum bb_path tx_path_en,
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enum bb_path rx_path,
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enum bb_path tx_path_sel_1ss);
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boolean
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config_phydm_parameter_init_8822b(struct dm_struct *dm,
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enum odm_parameter_init type);
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/* @======================================================================== */
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/* @These following functions can be used for PHY DM only*/
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boolean
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phydm_write_txagc_1byte_8822b(struct dm_struct *dm, u32 pw_idx,
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enum rf_path path, u8 hw_rate);
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void phydm_get_condi_num_acc_8822b(void *dm_void);
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u32 phydm_get_condi_num_8822b(struct dm_struct *dm);
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__iram_odm_func__
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void phydm_rxagc_switch_8822b(struct dm_struct *dm,
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boolean enable_rxagc_switch);
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boolean
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phydm_rfe_8822b_lps(struct dm_struct *dm, boolean enable_sw_rfe);
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/* @======================================================================== */
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#endif /* RTL8822B_SUPPORT == 1 */
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#endif /* @__INC_PHYDM_API_H_8822B__ */
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