/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __PHYDMRAINFO_H__
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#define __PHYDMRAINFO_H__
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/*#define RAINFO_VERSION "2.0" //2014.11.04*/
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/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/
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/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/
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/*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/
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/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/
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/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */
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#define RAINFO_VERSION "4.1" /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */
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#define H2C_0X42_LENGTH 5
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#define RA_FLOOR_UP_GAP 3
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#define RA_FLOOR_TABLE_SIZE 7
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#define ACTIVE_TP_THRESHOLD 150
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#define RA_RETRY_DESCEND_NUM 2
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#define RA_RETRY_LIMIT_LOW 4
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#define RA_RETRY_LIMIT_HIGH 32
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#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL
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#define RAINFO_STBC_STATE BIT1
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//#define RAINFO_LDPC_STATE BIT2
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#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection
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#define RAINFO_SHURTCUT_STATE BIT3
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#define RAINFO_SHURTCUT_FLAG BIT4
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#define RAINFO_INIT_RSSI_RATE_STATE BIT5
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#define RAINFO_BF_STATE BIT6
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#define RAINFO_BE_TX_STATE BIT7 // 1:TX
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#define RA_MASK_CCK 0xf
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#define RA_MASK_OFDM 0xff0
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#define RA_MASK_HT1SS 0xff000
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#define RA_MASK_HT2SS 0xff00000
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/*#define RA_MASK_MCS3SS */
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#define RA_MASK_HT4SS 0xff0
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#define RA_MASK_VHT1SS 0x3ff000
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#define RA_MASK_VHT2SS 0xffc00000
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#if(DM_ODM_SUPPORT_TYPE == ODM_AP)
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#define RA_FIRST_MACID 1
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#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#define RA_FIRST_MACID 0
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#define WIN_DEFAULT_PORT_MACID 0
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#define WIN_BT_PORT_MACID 2
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#else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
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#define RA_FIRST_MACID 0
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#endif
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#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit
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#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN)
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#define DM_RATR_STA_INIT 0
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#define DM_RATR_STA_HIGH 1
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#define DM_RATR_STA_MIDDLE 2
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#define DM_RATR_STA_LOW 3
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#define DM_RATR_STA_ULTRA_LOW 4
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#endif
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typedef enum _phydm_arfr_num {
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ARFR_0_RATE_ID = 0x9,
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ARFR_1_RATE_ID = 0xa,
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ARFR_2_RATE_ID = 0xb,
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ARFR_3_RATE_ID = 0xc,
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ARFR_4_RATE_ID = 0xd,
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ARFR_5_RATE_ID = 0xe
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} PHYDM_RA_ARFR_NUM_E;
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typedef enum _Phydm_ra_dbg_para {
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RADBG_PCR_TH_OFFSET = 0,
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RADBG_RTY_PENALTY = 1,
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RADBG_N_HIGH = 2,
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RADBG_N_LOW = 3,
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RADBG_TRATE_UP_TABLE = 4,
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RADBG_TRATE_DOWN_TABLE = 5,
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RADBG_TRYING_NECESSARY = 6,
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RADBG_TDROPING_NECESSARY = 7,
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RADBG_RATE_UP_RTY_RATIO = 8,
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RADBG_RATE_DOWN_RTY_RATIO = 9, //u8
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RADBG_DEBUG_MONITOR1 = 0xc,
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RADBG_DEBUG_MONITOR2 = 0xd,
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RADBG_DEBUG_MONITOR3 = 0xe,
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RADBG_DEBUG_MONITOR4 = 0xf,
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RADBG_DEBUG_MONITOR5 = 0x10,
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NUM_RA_PARA
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} PHYDM_RA_DBG_PARA_E;
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typedef enum PHYDM_WIRELESS_MODE {
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PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
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PHYDM_WIRELESS_MODE_A = 0x01,
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PHYDM_WIRELESS_MODE_B = 0x02,
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PHYDM_WIRELESS_MODE_G = 0x04,
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PHYDM_WIRELESS_MODE_AUTO = 0x08,
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PHYDM_WIRELESS_MODE_N_24G = 0x10,
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PHYDM_WIRELESS_MODE_N_5G = 0x20,
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PHYDM_WIRELESS_MODE_AC_5G = 0x40,
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PHYDM_WIRELESS_MODE_AC_24G = 0x80,
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PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
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PHYDM_WIRELESS_MODE_MAX = 0x800,
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PHYDM_WIRELESS_MODE_ALL = 0xFFFF
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} PHYDM_WIRELESS_MODE_E;
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typedef enum PHYDM_RATEID_IDX_ {
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PHYDM_BGN_40M_2SS = 0,
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PHYDM_BGN_40M_1SS = 1,
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PHYDM_BGN_20M_2SS = 2,
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PHYDM_BGN_20M_1SS = 3,
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PHYDM_GN_N2SS = 4,
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PHYDM_GN_N1SS = 5,
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PHYDM_BG = 6,
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PHYDM_G = 7,
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PHYDM_B_20M = 8,
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PHYDM_ARFR0_AC_2SS = 9,
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PHYDM_ARFR1_AC_1SS = 10,
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PHYDM_ARFR2_AC_2G_1SS = 11,
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PHYDM_ARFR3_AC_2G_2SS = 12,
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PHYDM_ARFR4_AC_3SS = 13,
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PHYDM_ARFR5_N_3SS = 14
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} PHYDM_RATEID_IDX_E;
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typedef enum _PHYDM_RF_TYPE_DEFINITION {
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PHYDM_RF_1T1R = 0,
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PHYDM_RF_1T2R,
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PHYDM_RF_2T2R,
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PHYDM_RF_2T2R_GREEN,
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PHYDM_RF_2T3R,
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PHYDM_RF_2T4R,
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PHYDM_RF_3T3R,
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PHYDM_RF_3T4R,
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PHYDM_RF_4T4R,
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PHYDM_RF_MAX_TYPE
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} PHYDM_RF_TYPE_DEF_E;
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typedef enum _PHYDM_BW {
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PHYDM_BW_20 = 0,
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PHYDM_BW_40,
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PHYDM_BW_80,
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PHYDM_BW_80_80,
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PHYDM_BW_160,
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PHYDM_BW_10,
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PHYDM_BW_5
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} PHYDM_BW_E;
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#if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA
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typedef struct _ODM_RA_Info_ {
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u1Byte RateID;
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u4Byte RateMask;
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u4Byte RAUseRate;
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u1Byte RateSGI;
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u1Byte RssiStaRA;
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u1Byte PreRssiStaRA;
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u1Byte SGIEnable;
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u1Byte DecisionRate;
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u1Byte PreRate;
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u1Byte HighestRate;
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u1Byte LowestRate;
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u4Byte NscUp;
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u4Byte NscDown;
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u2Byte RTY[5];
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u4Byte TOTAL;
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u2Byte DROP;
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u1Byte Active;
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u2Byte RptTime;
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u1Byte RAWaitingCounter;
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u1Byte RAPendingCounter;
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u1Byte RADropAfterDown;
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#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!
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u1Byte PTActive; // on or off
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u1Byte PTTryState; // 0 trying state, 1 for decision state
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u1Byte PTStage; // 0~6
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u1Byte PTStopCount; //Stop PT counter
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u1Byte PTPreRate; // if rate change do PT
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u1Byte PTPreRssi; // if RSSI change 5% do PT
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u1Byte PTModeSS; // decide whitch rate should do PT
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u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
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u1Byte PTSmoothFactor;
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#endif
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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u1Byte RateDownCounter;
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u1Byte RateUpCounter;
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u1Byte RateDirection;
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u1Byte BoundingType;
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u1Byte BoundingCounter;
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u1Byte BoundingLearningTime;
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u1Byte RateDownStartTime;
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#endif
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} ODM_RA_INFO_T, *PODM_RA_INFO_T;
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#endif
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typedef struct _Rate_Adaptive_Table_ {
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u1Byte firstconnect;
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#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
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BOOLEAN PT_collision_pre;
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#endif
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#if (defined(CONFIG_RA_DBG_CMD))
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BOOLEAN is_ra_dbg_init;
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u1Byte RTY_P[ODM_NUM_RATE_IDX];
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u1Byte RTY_P_default[ODM_NUM_RATE_IDX];
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BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX];
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u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];
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u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];
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BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
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u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];
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u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];
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BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
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BOOLEAN RA_Para_feedback_req;
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u1Byte para_idx;
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u1Byte rate_idx;
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u1Byte value;
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u2Byte value_16;
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u1Byte rate_length;
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#endif
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u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
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u1Byte highest_client_tx_order;
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u2Byte highest_client_tx_rate_order;
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u1Byte power_tracking_flag;
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u1Byte RA_threshold_offset;
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u1Byte RA_offset_direction;
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#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
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u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
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u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
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u1Byte retry_descend_num;
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u1Byte retrylimit_low;
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u1Byte retrylimit_high;
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#endif
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} RA_T, *pRA_T;
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typedef struct _ODM_RATE_ADAPTIVE {
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u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
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u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
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u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
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u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
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#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC
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BOOLEAN bLowerRtsRate;
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#endif
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#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
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u1Byte RtsThres;
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#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
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BOOLEAN bUseLdpc;
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#else
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u1Byte UltraLowRSSIThresh;
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u4Byte LastRATR; // RATR Register Content
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#endif
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} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
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#if (defined(CONFIG_RA_DBG_CMD))
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VOID
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odm_RA_debug(
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IN PVOID pDM_VOID,
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IN u4Byte *const dm_value
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);
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VOID
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odm_RA_ParaAdjust_init(
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IN PVOID pDM_VOID
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);
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#else
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VOID
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phydm_RA_debug_PCR(
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IN PVOID pDM_VOID,
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IN u4Byte *const dm_value,
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IN u4Byte *_used,
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OUT char *output,
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IN u4Byte *_out_len
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);
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#endif
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VOID
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ODM_C2HRaParaReportHandler(
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IN PVOID pDM_VOID,
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IN pu1Byte CmdBuf,
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IN u1Byte CmdLen
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);
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VOID
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odm_RA_ParaAdjust(
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IN PVOID pDM_VOID
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);
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VOID
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phydm_ra_dynamic_retry_count(
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IN PVOID pDM_VOID
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);
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VOID
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phydm_ra_dynamic_retry_limit(
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IN PVOID pDM_VOID
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);
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VOID
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phydm_ra_dynamic_rate_id_on_assoc(
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IN PVOID pDM_VOID,
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IN u1Byte wireless_mode,
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IN u1Byte init_rate_id
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);
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VOID
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phydm_print_rate(
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IN PVOID pDM_VOID,
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IN u1Byte rate,
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IN u4Byte dbg_component
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);
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VOID
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phydm_c2h_ra_report_handler(
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IN PVOID pDM_VOID,
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IN pu1Byte CmdBuf,
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IN u1Byte CmdLen
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);
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u1Byte
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phydm_rate_order_compute(
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IN PVOID pDM_VOID,
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IN u1Byte rate_idx
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);
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VOID
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phydm_ra_info_watchdog(
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IN PVOID pDM_VOID
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);
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VOID
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phydm_ra_info_init(
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IN PVOID pDM_VOID
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);
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VOID
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odm_RSSIMonitorInit(
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IN PVOID pDM_VOID
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);
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VOID
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odm_RSSIMonitorCheck(
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IN PVOID pDM_VOID
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);
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VOID
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phydm_initRaInfo(
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IN PVOID pDM_VOID
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);
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u1Byte
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phydm_vht_en_mapping(
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IN PVOID pDM_VOID,
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IN u4Byte WirelessMode
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);
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u1Byte
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phydm_rate_id_mapping(
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IN PVOID pDM_VOID,
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IN u4Byte WirelessMode,
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IN u1Byte RfType,
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IN u1Byte bw
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);
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VOID
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phydm_UpdateHalRAMask(
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IN PVOID pDM_VOID,
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IN u4Byte wirelessMode,
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IN u1Byte RfType,
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IN u1Byte BW,
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IN u1Byte MimoPs_enable,
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IN u1Byte disable_cck_rate,
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IN u4Byte *ratr_bitmap_msb_in,
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IN u4Byte *ratr_bitmap_in,
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IN u1Byte tx_rate_level
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);
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VOID
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odm_RateAdaptiveMaskInit(
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IN PVOID pDM_VOID
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);
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VOID
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odm_RefreshRateAdaptiveMask(
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IN PVOID pDM_VOID
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);
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VOID
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odm_RefreshRateAdaptiveMaskMP(
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IN PVOID pDM_VOID
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);
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VOID
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odm_RefreshRateAdaptiveMaskCE(
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IN PVOID pDM_VOID
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);
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VOID
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odm_RefreshRateAdaptiveMaskAPADSL(
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IN PVOID pDM_VOID
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);
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u1Byte
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phydm_RA_level_decision(
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IN PVOID pDM_VOID,
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IN u4Byte rssi,
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IN u1Byte Ratr_State
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);
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BOOLEAN
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ODM_RAStateCheck(
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IN PVOID pDM_VOID,
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IN s4Byte RSSI,
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IN BOOLEAN bForceUpdate,
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OUT pu1Byte pRATRState
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);
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VOID
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odm_RefreshBasicRateMask(
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IN PVOID pDM_VOID
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);
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VOID
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ODM_RAPostActionOnAssoc(
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IN PVOID pDM_Odm
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);
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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u1Byte
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odm_Find_RTS_Rate(
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IN PVOID pDM_VOID,
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IN u1Byte Tx_Rate,
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IN BOOLEAN bErpProtect
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);
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VOID
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ODM_UpdateNoisyState(
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IN PVOID pDM_VOID,
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IN BOOLEAN bNoisyStateFromC2H
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);
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VOID
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phydm_update_pwr_track(
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IN PVOID pDM_VOID,
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IN u1Byte Rate
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);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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s4Byte
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phydm_FindMinimumRSSI(
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IN PDM_ODM_T pDM_Odm,
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IN PADAPTER pAdapter,
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IN OUT BOOLEAN *pbLink_temp
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);
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VOID
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ODM_UpdateInitRateWorkItemCallback(
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IN PVOID pContext
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);
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VOID
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odm_RSSIDumpToRegister(
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IN PVOID pDM_VOID
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);
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VOID
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odm_RefreshLdpcRtsMP(
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IN PADAPTER pAdapter,
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IN PDM_ODM_T pDM_Odm,
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IN u1Byte mMacId,
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IN u1Byte IOTPeer,
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IN s4Byte UndecoratedSmoothedPWDB
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);
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#if 0
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VOID
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ODM_DynamicARFBSelect(
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IN PVOID pDM_VOID,
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IN u1Byte rate,
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IN BOOLEAN Collision_State
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);
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#endif
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VOID
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ODM_RateAdaptiveStateApInit(
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IN PVOID PADAPTER_VOID,
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IN PRT_WLAN_STA pEntry
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);
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#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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static void
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FindMinimumRSSI(
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IN PADAPTER pAdapter
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);
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u8Byte
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PhyDM_Get_Rate_Bitmap_Ex(
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IN PVOID pDM_VOID,
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IN u4Byte macid,
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IN u8Byte ra_mask,
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IN u1Byte rssi_level,
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OUT u8Byte *dm_RA_Mask,
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OUT u1Byte *dm_RteID
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);
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u4Byte
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ODM_Get_Rate_Bitmap(
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IN PVOID pDM_VOID,
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IN u4Byte macid,
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IN u4Byte ra_mask,
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IN u1Byte rssi_level
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);
|
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void phydm_ra_rssi_rpt_wk(PVOID pContext);
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#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
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#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
|
VOID
|
phydm_gen_ramask_h2c_AP(
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IN PVOID pDM_VOID,
|
IN struct rtl8192cd_priv *priv,
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IN PSTA_INFO_T *pEntry,
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IN u1Byte rssi_level
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);
|
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#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/
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#endif /*#ifndef __ODMRAINFO_H__*/
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