/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2016 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __INC_PHYDM_API_H_8821C__
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#define __INC_PHYDM_API_H_8821C__
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#if (RTL8821C_SUPPORT == 1)
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#define PHY_CONFIG_VERSION_8821C "3.1.27" /*2017.08.08 (HW user guide version: R03, SW user guide version: R01, Modification: R27)*/
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#define INVALID_RF_DATA 0xffffffff
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#define INVALID_TXAGC_DATA 0xff
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#define config_phydm_read_rf_check_8821c(data) (data != INVALID_RF_DATA)
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#define config_phydm_read_txagc_check_8821c(data) (data != INVALID_TXAGC_DATA)
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#define PSD_VAL_NUM_8821C 5
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#define PSD_SMP_NUM_8821C 3
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#define FREQ_PT_5G_NUM_8821C 3
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enum rf_set_8821c {
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SWITCH_TO_BTG = 0x0,
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SWITCH_TO_WLG = 0x1,
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SWITCH_TO_WLA = 0x2,
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SWITCH_TO_BT = 0x3
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};
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enum ant_num_8821c {
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SWITCH_TO_ANT1 = 0x0,
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SWITCH_TO_ANT2 = 0x1
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};
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enum ant_num_map_8821c {
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BOTH_AVAILABLE = 0x1,
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ONLY_ANT1 = 0x2,
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ONLY_ANT2 = 0x3,
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DONT_CARE = 0x4
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};
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s8 phydm_cck_rssi_8821c(struct dm_struct *dm, u8 lna_idx, u8 vga_idx);
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u32 config_phydm_read_rf_reg_8821c(struct dm_struct *dm, enum rf_path path,
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u32 reg_addr, u32 bit_mask);
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boolean
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config_phydm_write_rf_reg_8821c(struct dm_struct *dm, enum rf_path path,
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u32 reg_addr, u32 bit_mask, u32 data);
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boolean
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config_phydm_write_txagc_8821c(struct dm_struct *dm, u32 power_index,
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enum rf_path path, u8 hw_rate);
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u8 config_phydm_read_txagc_8821c(struct dm_struct *dm, enum rf_path path,
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u8 hw_rate);
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boolean
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config_phydm_switch_band_8821c(struct dm_struct *dm, u8 central_ch);
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boolean
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config_phydm_switch_channel_8821c(struct dm_struct *dm, u8 central_ch);
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boolean
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config_phydm_switch_bandwidth_8821c(struct dm_struct *dm, u8 primary_ch_idx,
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enum channel_width bandwidth);
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boolean
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config_phydm_switch_channel_bw_8821c(struct dm_struct *dm, u8 central_ch,
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u8 primary_ch_idx,
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enum channel_width bandwidth);
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boolean
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config_phydm_trx_mode_8821c(struct dm_struct *dm, enum bb_path tx_path,
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enum bb_path rx_path, boolean is_tx2_path);
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boolean
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config_phydm_parameter_init_8821c(struct dm_struct *dm,
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enum odm_parameter_init type);
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void config_phydm_switch_rf_set_8821c(struct dm_struct *dm, u8 rf_set);
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void config_phydm_set_ant_path(struct dm_struct *dm, u8 rf_set, u8 ant_num);
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/* ======================================================================== */
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/* These following functions can be used for PHY DM only*/
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boolean
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phydm_write_txagc_1byte_8821c(struct dm_struct *dm, u32 power_index,
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enum rf_path path, u8 hw_rate);
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void phydm_init_hw_info_by_rfe_type_8821c(struct dm_struct *dm);
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void phydm_set_gnt_state_8821c(struct dm_struct *dm, boolean gnt_wl_state,
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boolean gnt_bt_state);
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/* ======================================================================== */
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u32 query_phydm_trx_capability_8821c(struct dm_struct *dm);
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u32 query_phydm_stbc_capability_8821c(struct dm_struct *dm);
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u32 query_phydm_ldpc_capability_8821c(struct dm_struct *dm);
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u32 query_phydm_txbf_parameters_8821c(struct dm_struct *dm);
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u32 query_phydm_txbf_capability_8821c(struct dm_struct *dm);
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u8 query_phydm_default_rf_set_8821c(struct dm_struct *dm);
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u8 query_phydm_current_rf_set_8821c(struct dm_struct *dm);
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u8 query_phydm_rfetype_8821c(struct dm_struct *dm);
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u8 query_phydm_current_ant_num_8821c(struct dm_struct *dm);
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u8 query_phydm_ant_num_map_8821c(struct dm_struct *dm);
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#endif /* RTL8821C_SUPPORT == 1 */
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#endif /* __INC_PHYDM_API_H_8821C__ */
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