/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __ODM_DBG_H__
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#define __ODM_DBG_H__
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/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
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/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
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/*#define DEBUG_VERSION "1.3"*/ /*2016.04.28 YuChen*/
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#define DEBUG_VERSION "1.4" /*2017.03.13 Dino*/
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/* -----------------------------------------------------------------------------
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* Define the debug levels
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*
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* 1. DBG_TRACE and DBG_LOUD are used for normal cases.
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* So that, they can help SW engineer to develope or trace states changed
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* and also help HW enginner to trace every operation to and from HW,
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* e.g IO, Tx, Rx.
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*
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* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
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* which help us to debug SW or HW.
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*
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* -----------------------------------------------------------------------------
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*
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* Never used in a call to ODM_RT_TRACE()!
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* */
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#define ODM_DBG_OFF 1
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/*
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* Fatal bug.
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* For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
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* resource allocation failed, unexpected HW behavior, HW BUG and so on.
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* */
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#define ODM_DBG_SERIOUS 2
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/*
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* Abnormal, rare, or unexpeted cases.
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* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
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* */
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#define ODM_DBG_WARNING 3
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/*
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* Normal case with useful information about current SW or HW state.
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* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
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* SW protocol state change, dynamic mechanism state change and so on.
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* */
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#define ODM_DBG_LOUD 4
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/*
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* Normal case with detail execution flow or information.
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* */
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#define ODM_DBG_TRACE 5
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/*FW DBG MSG*/
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#define RATE_DECISION BIT(0)
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#define INIT_RA_TABLE BIT(1)
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#define RATE_UP BIT(2)
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#define RATE_DOWN BIT(3)
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#define TRY_DONE BIT(4)
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#define RA_H2C BIT(5)
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#define F_RATE_AP_RPT BIT(7)
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/* -----------------------------------------------------------------------------
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* Define the tracing components
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*
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* -----------------------------------------------------------------------------
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*BB FW Functions*/
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#define PHYDM_FW_COMP_RA BIT(0)
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#define PHYDM_FW_COMP_MU BIT(1)
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#define PHYDM_FW_COMP_PATH_DIV BIT(2)
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#define PHYDM_FW_COMP_PT BIT(3)
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/*------------------------Export Marco Definition---------------------------*/
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#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#define dbg_print DbgPrint
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#define dcmd_printf DCMD_Printf
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#define dcmd_scanf DCMD_Scanf
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#define RT_PRINTK dbg_print
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#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
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#define dbg_print(args...)
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#define RT_PRINTK(fmt, args...) \
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RT_TRACE(((struct rtl_priv *)p_dm->adapter), \
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COMP_PHYDM, DBG_DMESG, fmt, ## args)
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#define RT_DISP(dbgtype, dbgflag, printstr)
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#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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#define dbg_print printk
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#define RT_PRINTK(fmt, args...) dbg_print(fmt, ## args)
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#define RT_DISP(dbgtype, dbgflag, printstr)
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#else
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#define dbg_print panic_printk
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/*#define RT_PRINTK(fmt, args...) dbg_print("%s(): " fmt, __FUNCTION__, ## args);*/
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#define RT_PRINTK(args...) dbg_print(args)
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#endif
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#ifndef ASSERT
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#define ASSERT(expr)
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#endif
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#if DBG
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#define PHYDM_DBG(p_dm, comp, fmt) \
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do { \
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if ((comp) & (p_dm->debug_components)) { \
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\
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dbg_print("[PHYDM] "); \
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RT_PRINTK fmt; \
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} \
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} while (0)
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#define PHYDM_DBG_F(p_dm, comp, fmt) do {\
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if ((comp) & p_dm->debug_components) { \
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\
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RT_PRINTK fmt; \
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} \
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} while (0)
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#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr) do {\
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if ((comp) & p_dm->debug_components) { \
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\
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int __i; \
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u8 *__ptr = (u8 *)ptr; \
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dbg_print("[PHYDM] "); \
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dbg_print(title_str); \
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dbg_print(" "); \
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for (__i = 0; __i < 6; __i++) \
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dbg_print("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \
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dbg_print("\n"); \
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} \
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} while (0)
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#define ODM_RT_TRACE(p_dm, comp, level, fmt) \
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do { \
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if (((comp) & p_dm->debug_components) && (level <= p_dm->debug_level || level == ODM_DBG_SERIOUS)) { \
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\
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if (p_dm->support_ic_type == ODM_RTL8188E) \
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dbg_print("[PhyDM-8188E] "); \
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else if (p_dm->support_ic_type == ODM_RTL8192E) \
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dbg_print("[PhyDM-8192E] "); \
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else if (p_dm->support_ic_type == ODM_RTL8812) \
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dbg_print("[PhyDM-8812A] "); \
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else if (p_dm->support_ic_type == ODM_RTL8821) \
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dbg_print("[PhyDM-8821A] "); \
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else if (p_dm->support_ic_type == ODM_RTL8814A) \
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dbg_print("[PhyDM-8814A] "); \
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else if (p_dm->support_ic_type == ODM_RTL8703B) \
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dbg_print("[PhyDM-8703B] "); \
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else if (p_dm->support_ic_type == ODM_RTL8822B) \
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dbg_print("[PhyDM-8822B] "); \
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else if (p_dm->support_ic_type == ODM_RTL8188F) \
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dbg_print("[PhyDM-8188F] "); \
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RT_PRINTK fmt; \
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} \
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} while (0)
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#else
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#define PHYDM_DBG(p_dm, comp, fmt)
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#define PHYDM_DBG_F(p_dm, comp, fmt)
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#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr)
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#define ODM_RT_TRACE(p_dm, comp, level, fmt)
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#endif
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#define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/
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#define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/
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#define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/
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#define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#define PHYDM_DBGPRINT 0
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#define PHYDM_SSCANF(x, y, z) dcmd_scanf(x, y, z)
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#define PHYDM_VAST_INFO_SNPRINTF PHYDM_SNPRINTF
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#if (PHYDM_DBGPRINT == 1)
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#define PHYDM_SNPRINTF(msg) \
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do {\
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rsprintf msg;\
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dbg_print(output);\
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} while (0)
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#else
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#define PHYDM_SNPRINTF(msg) \
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do {\
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rsprintf msg;\
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dcmd_printf(output);\
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} while (0)
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#endif
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#else
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#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__)
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#define PHYDM_DBGPRINT 0
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#else
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#define PHYDM_DBGPRINT 1
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#endif
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#define MAX_ARGC 20
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#define MAX_ARGV 16
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#define DCMD_DECIMAL "%d"
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#define DCMD_CHAR "%c"
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#define DCMD_HEX "%x"
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#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z)
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#define PHYDM_VAST_INFO_SNPRINTF(msg)\
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do {\
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snprintf msg;\
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dbg_print(output);\
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} while (0)
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#if (PHYDM_DBGPRINT == 1)
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#define PHYDM_SNPRINTF(msg)\
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do {\
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snprintf msg;\
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dbg_print(output);\
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} while (0)
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#else
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#define PHYDM_SNPRINTF(msg)\
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do {\
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if (out_len > used)\
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used += snprintf msg;\
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} while (0)
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#endif
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#endif
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void
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phydm_init_debug_setting(
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struct PHY_DM_STRUCT *p_dm
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);
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void
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phydm_bb_dbg_port_header_sel(
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void *p_dm_void,
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u32 header_idx
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);
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u8
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phydm_set_bb_dbg_port(
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void *p_dm_void,
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u8 curr_dbg_priority,
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u32 debug_port
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);
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void
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phydm_release_bb_dbg_port(
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void *p_dm_void
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);
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u32
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phydm_get_bb_dbg_port_value(
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void *p_dm_void
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);
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void
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phydm_reset_rx_rate_distribution(
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struct PHY_DM_STRUCT *p_dm_odm
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);
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void
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phydm_rx_rate_distribution
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(
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void *p_dm_void
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);
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void
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phydm_get_avg_phystatus_val
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(
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void *p_dm_void
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);
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void
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phydm_get_phy_statistic(
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void *p_dm_void
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);
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void
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phydm_basic_dbg_message(
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void *p_dm_void
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);
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void
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phydm_basic_profile(
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void *p_dm_void,
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u32 *_used,
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char *output,
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u32 *_out_len
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);
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
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s32
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phydm_cmd(
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struct PHY_DM_STRUCT *p_dm,
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char *input,
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u32 in_len,
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u8 flag,
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char *output,
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u32 out_len
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);
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#endif
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void
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phydm_cmd_parser(
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struct PHY_DM_STRUCT *p_dm,
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char input[][16],
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u32 input_num,
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u8 flag,
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char *output,
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u32 out_len
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);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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void phydm_sbd_check(
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struct PHY_DM_STRUCT *p_dm
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);
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void phydm_sbd_callback(
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struct timer_list *p_timer
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);
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void phydm_sbd_workitem_callback(
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void *p_context
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);
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#endif
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void
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phydm_fw_trace_en_h2c(
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void *p_dm_void,
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boolean enable,
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u32 fw_debug_component,
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u32 monitor_mode,
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u32 macid
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);
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void
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phydm_fw_trace_handler(
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void *p_dm_void,
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u8 *cmd_buf,
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u8 cmd_len
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);
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void
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phydm_fw_trace_handler_code(
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void *p_dm_void,
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u8 *buffer,
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u8 cmd_len
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);
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void
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phydm_fw_trace_handler_8051(
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void *p_dm_void,
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u8 *cmd_buf,
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u8 cmd_len
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);
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#endif /* __ODM_DBG_H__ */
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