/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __PHYDMIQK_H__
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#define __PHYDMIQK_H__
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/*--------------------------Define Parameters-------------------------------*/
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#define LOK_delay 1
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#define WBIQK_delay 10
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#define TX_IQK 0
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#define RX_IQK 1
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#define TXIQK 0
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#define RXIQK1 1
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#define RXIQK2 2
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#define kcount_limit_80m 2
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#define kcount_limit_others 4
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#define rxiqk_gs_limit 4
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#define NUM 4
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/*---------------------------End Define Parameters-------------------------------*/
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struct _IQK_INFORMATION {
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boolean LOK_fail[NUM];
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boolean IQK_fail[2][NUM];
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u32 iqc_matrix[2][NUM];
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u8 iqk_times;
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u32 rf_reg18;
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u32 lna_idx;
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u8 rxiqk_step;
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u8 tmp1bcc;
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u8 kcount;
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u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
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boolean rfk_forbidden;
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#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
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u32 iqk_channel[2];
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boolean IQK_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
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u32 IQK_CFIR_real[3][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ /*channel index = 2 is just for debug*/
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u32 IQK_CFIR_imag[3][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ /*channel index = 2 is just for debug*/
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u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
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u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
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u8 RXIQK_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
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u32 LOK_IDAC[2][4]; /*channel / path*/
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u16 RXIQK_AGC[2][4]; /*channel / path*/
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u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
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u32 txgap_result[8]; /*txagpK result */
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u32 tmp_GNTWL;
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boolean is_BTG;
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boolean isbnd;
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boolean is_reload;
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boolean segment_iqk;
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boolean is_hwtx;
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boolean xym_read;
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boolean trximr_enable;
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u32 rx_xym[2][10];
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u32 tx_xym[2][10];
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u32 gs1_xym[2][6];
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u32 gs2_xym[2][6];
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u32 rxk1_xym[2][6];
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#endif
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};
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#endif
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