/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Broadcom SiliconBackplane ARM definitions
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*
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* Copyright (C) 1999-2019, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: sbhndarm.h 799498 2019-01-16 06:02:27Z $
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*/
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#ifndef _sbhndarm_h_
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#define _sbhndarm_h_
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#ifndef _LANGUAGE_ASSEMBLY
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif /* PAD */
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/* cortex-m3 */
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typedef volatile struct {
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uint32 corecontrol; /* 0x0 */
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uint32 corestatus; /* 0x4 */
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uint32 PAD[1];
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uint32 biststatus; /* 0xc */
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uint32 nmiisrst; /* 0x10 */
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uint32 nmimask; /* 0x14 */
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uint32 isrmask; /* 0x18 */
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uint32 PAD[1];
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uint32 resetlog; /* 0x20 */
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uint32 gpioselect; /* 0x24 */
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uint32 gpioenable; /* 0x28 */
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uint32 PAD[1];
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uint32 bpaddrlo; /* 0x30 */
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uint32 bpaddrhi; /* 0x34 */
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uint32 bpdata; /* 0x38 */
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uint32 bpindaccess; /* 0x3c */
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uint32 ovlidx; /* 0x40 */
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uint32 ovlmatch; /* 0x44 */
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uint32 ovladdr; /* 0x48 */
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uint32 PAD[13];
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uint32 bwalloc; /* 0x80 */
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uint32 PAD[3];
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uint32 cyclecnt; /* 0x90 */
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uint32 inttimer; /* 0x94 */
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uint32 intmask; /* 0x98 */
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uint32 intstatus; /* 0x9c */
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uint32 PAD[80];
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uint32 clk_ctl_st; /* 0x1e0 */
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uint32 PAD[1];
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uint32 powerctl; /* 0x1e8 */
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} cm3regs_t;
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#define ARM_CM3_REG(regs, reg) (&((cm3regs_t *)regs)->reg)
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/* cortex-R4 */
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typedef volatile struct {
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uint32 corecontrol; /* 0x0 */
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uint32 corecapabilities; /* 0x4 */
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uint32 corestatus; /* 0x8 */
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uint32 biststatus; /* 0xc */
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uint32 nmiisrst; /* 0x10 */
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uint32 nmimask; /* 0x14 */
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uint32 isrmask; /* 0x18 */
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uint32 swintreg; /* 0x1C */
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uint32 intstatus; /* 0x20 */
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uint32 intmask; /* 0x24 */
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uint32 cyclecnt; /* 0x28 */
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uint32 inttimer; /* 0x2c */
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uint32 gpioselect; /* 0x30 */
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uint32 gpioenable; /* 0x34 */
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uint32 PAD[2];
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uint32 bankidx; /* 0x40 */
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uint32 bankinfo; /* 0x44 */
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uint32 bankstbyctl; /* 0x48 */
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uint32 bankpda; /* 0x4c */
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uint32 PAD[6];
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uint32 tcampatchctrl; /* 0x68 */
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uint32 tcampatchtblbaseaddr; /* 0x6c */
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uint32 tcamcmdreg; /* 0x70 */
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uint32 tcamdatareg; /* 0x74 */
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uint32 tcambankxmaskreg; /* 0x78 */
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uint32 PAD[89];
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uint32 clk_ctl_st; /* 0x1e0 */
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uint32 PAD[1];
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uint32 powerctl; /* 0x1e8 */
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} cr4regs_t;
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#define ARM_CR4_REG(regs, reg) (&((cr4regs_t *)regs)->reg)
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/* cortex-A7 */
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typedef volatile struct {
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uint32 corecontrol; /* 0x0 */
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uint32 corecapabilities; /* 0x4 */
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uint32 corestatus; /* 0x8 */
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uint32 tracecontrol; /* 0xc */
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uint32 PAD[8];
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uint32 gpioselect; /* 0x30 */
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uint32 gpioenable; /* 0x34 */
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uint32 PAD[106];
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uint32 clk_ctl_st; /* 0x1e0 */
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uint32 PAD[1];
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uint32 powerctl; /* 0x1e8 */
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} ca7regs_t;
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#define ARM_CA7_REG(regs, reg) (&((ca7regs_t *)regs)->reg)
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#if defined(__ARM_ARCH_7M__)
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#define ARMREG(regs, reg) ARM_CM3_REG(regs, reg)
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#endif /* __ARM_ARCH_7M__ */
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#if defined(__ARM_ARCH_7R__)
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#define ARMREG(regs, reg) ARM_CR4_REG(regs, reg)
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#endif /* __ARM_ARCH_7R__ */
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#if defined(__ARM_ARCH_7A__)
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#define ARMREG(regs, reg) ARM_CA7_REG(regs, reg)
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#endif /* __ARM_ARCH_7A__ */
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#endif /* _LANGUAGE_ASSEMBLY */
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#endif /* _sbhndarm_h_ */
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