/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Linux DHD Bus Module for PCIE
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*
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* Copyright (C) 1999-2019, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: dhd_pcie.h 606080 2015-12-14 09:31:57Z $
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*/
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#ifndef dhd_pcie_h
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#define dhd_pcie_h
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#include <bcmpcie.h>
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#include <hnd_cons.h>
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#ifdef SUPPORT_LINKDOWN_RECOVERY
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#ifdef CONFIG_ARCH_MSM
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#if defined(CONFIG_ARCH_MSM8994) || defined(CONFIG_ARCH_MSM8996)
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#include <linux/msm_pcie.h>
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#else
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#include <mach/msm_pcie.h>
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#endif /* CONFIG_ARCH_MSM8994 */
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#endif /* CONFIG_ARCH_MSM */
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#endif /* SUPPORT_LINKDOWN_RECOVERY */
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/* defines */
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#define PCMSGBUF_HDRLEN 0
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#define DONGLE_REG_MAP_SIZE (32 * 1024)
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#define DONGLE_TCM_MAP_SIZE (4096 * 1024)
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#define DONGLE_MIN_MEMSIZE (128 *1024)
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#ifdef DHD_DEBUG
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#define DHD_PCIE_SUCCESS 0
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#define DHD_PCIE_FAILURE 1
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#endif /* DHD_DEBUG */
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#define REMAP_ENAB(bus) ((bus)->remap)
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#define REMAP_ISADDR(bus, a) (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
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/*
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* Router with 4366 can have 128 stations and 16 BSS,
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* hence (128 stations x 4 access categories for ucast) + 16 bc/mc flowrings
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*/
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#define MAX_DHD_TX_FLOWS 320
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/* user defined data structures */
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/* Device console log buffer state */
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#define CONSOLE_LINE_MAX 192
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#define CONSOLE_BUFFER_MAX (8 * 1024)
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#ifndef MAX_CNTL_D3ACK_TIMEOUT
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#define MAX_CNTL_D3ACK_TIMEOUT 2
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#endif /* MAX_CNTL_D3ACK_TIMEOUT */
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#ifdef DHD_DEBUG
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typedef struct dhd_console {
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uint count; /* Poll interval msec counter */
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uint log_addr; /* Log struct address (fixed) */
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hnd_log_t log; /* Log struct (host copy) */
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uint bufsize; /* Size of log buffer */
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uint8 *buf; /* Log buffer (host copy) */
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uint last; /* Last buffer read index */
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} dhd_console_t;
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#endif /* DHD_DEBUG */
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typedef struct ring_sh_info {
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uint32 ring_mem_addr;
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uint32 ring_state_w;
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uint32 ring_state_r;
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} ring_sh_info_t;
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typedef struct dhd_bus {
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dhd_pub_t *dhd;
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struct pci_dev *dev; /* pci device handle */
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dll_t const_flowring; /* constructed list of tx flowring queues */
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si_t *sih; /* Handle for SI calls */
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char *vars; /* Variables (from CIS and/or other) */
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uint varsz; /* Size of variables buffer */
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uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
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sbpcieregs_t *reg; /* Registers for PCIE core */
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uint armrev; /* CPU core revision */
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uint ramrev; /* SOCRAM core revision */
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uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
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uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
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uint32 srmemsize; /* Size of SRMEM */
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uint32 bus; /* gSPI or SDIO bus */
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uint32 intstatus; /* Intstatus bits (events) pending */
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bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
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bool fcstate; /* State of dongle flow-control */
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uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
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char *fw_path; /* module_param: path to firmware image */
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char *nv_path; /* module_param: path to nvram vars file */
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#ifdef CACHE_FW_IMAGES
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int processed_nvram_params_len; /* Modified len of NVRAM info */
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#endif
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#if defined(CUSTOMER_HW_31_2)
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char *nvram_params; /* user specified nvram params. */
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int nvram_params_len;
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#endif
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struct pktq txq; /* Queue length used for flow-control */
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bool intr; /* Use interrupts */
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bool ipend; /* Device interrupt is pending */
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bool intdis; /* Interrupts disabled by isr */
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uint intrcount; /* Count of device interrupt callbacks */
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uint lastintrs; /* Count as of last watchdog timer */
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#ifdef DHD_DEBUG
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dhd_console_t console; /* Console output polling support */
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uint console_addr; /* Console address from shared struct */
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#endif /* DHD_DEBUG */
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bool alp_only; /* Don't use HT clock (ALP only) */
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bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
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* Available with socram rev 16
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* Remap region not DMA-able
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*/
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uint32 resetinstr;
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uint32 dongle_ram_base;
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ulong shared_addr;
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pciedev_shared_t *pcie_sh;
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bool bus_flowctrl;
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uint32 dma_rxoffset;
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volatile char *regs; /* pci device memory va */
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volatile char *tcm; /* pci device memory va */
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osl_t *osh;
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uint32 nvram_csm; /* Nvram checksum */
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uint16 pollrate;
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uint16 polltick;
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uint32 *pcie_mb_intr_addr;
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void *pcie_mb_intr_osh;
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bool sleep_allowed;
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/* version 3 shared struct related info start */
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ring_sh_info_t ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
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uint8 h2d_ring_count;
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uint8 d2h_ring_count;
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uint32 ringmem_ptr;
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uint32 ring_state_ptr;
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uint32 d2h_dma_scratch_buffer_mem_addr;
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uint32 h2d_mb_data_ptr_addr;
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uint32 d2h_mb_data_ptr_addr;
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/* version 3 shared struct related info end */
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uint32 def_intmask;
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bool ltrsleep_on_unload;
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uint wait_for_d3_ack;
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uint32 max_sub_queues;
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uint32 rw_index_sz;
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bool db1_for_mb;
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bool suspended;
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dhd_timeout_t doorbell_timer;
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bool device_wake_state;
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#ifdef PCIE_OOB
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bool oob_enabled;
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#endif /* PCIE_OOB */
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#ifdef SUPPORT_LINKDOWN_RECOVERY
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#ifdef CONFIG_ARCH_MSM
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struct msm_pcie_register_event pcie_event;
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uint8 islinkdown;
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#endif /* CONFIG_ARCH_MSM */
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#endif /* SUPPORT_LINKDOWN_RECOVERY */
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uint32 d3_inform_cnt;
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uint32 d0_inform_cnt;
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uint32 d0_inform_in_use_cnt;
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uint8 force_suspend;
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} dhd_bus_t;
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/* function declarations */
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extern uint32* dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
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extern int dhdpcie_bus_register(void);
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extern void dhdpcie_bus_unregister(void);
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extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
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extern struct dhd_bus* dhdpcie_bus_attach(osl_t *osh,
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volatile char *regs, volatile char *tcm, void *pci_dev);
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extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);
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extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data);
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extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus);
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extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
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extern void dhdpcie_bus_release(struct dhd_bus *bus);
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extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
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extern void dhdpcie_free_irq(dhd_bus_t *bus);
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extern void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value);
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extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state);
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extern int dhdpcie_pci_suspend_resume(struct dhd_bus *bus, bool state);
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extern bool dhdpcie_tcm_valid(dhd_bus_t *bus);
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#ifndef BCMPCIE_OOB_HOST_WAKE
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extern void dhdpcie_pme_active(osl_t *osh, bool enable);
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#endif /* !BCMPCIE_OOB_HOST_WAKE */
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extern bool dhdpcie_pme_cap(osl_t *osh);
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extern uint32 dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val);
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extern uint8 dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val);
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extern int dhdpcie_start_host_pcieclock(dhd_bus_t *bus);
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extern int dhdpcie_stop_host_pcieclock(dhd_bus_t *bus);
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extern int dhdpcie_disable_device(dhd_bus_t *bus);
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extern int dhdpcie_enable_device(dhd_bus_t *bus);
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extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
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extern void dhdpcie_free_resource(dhd_bus_t *bus);
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extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
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#ifdef BCMPCIE_OOB_HOST_WAKE
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extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
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extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
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extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
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#endif /* BCMPCIE_OOB_HOST_WAKE */
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#ifdef PCIE_OOB
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extern void dhd_oob_set_bt_reg_on(struct dhd_bus *bus, bool val);
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extern int dhd_oob_get_bt_reg_on(struct dhd_bus *bus);
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#endif /* PCIE_OOB */
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#ifdef USE_EXYNOS_PCIE_RC_PMPATCH
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#if defined(CONFIG_MACH_UNIVERSAL5433)
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#define SAMSUNG_PCIE_DEVICE_ID 0xa5e3
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#define SAMSUNG_PCIE_CH_NUM
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#elif defined(CONFIG_MACH_UNIVERSAL7420)
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#define SAMSUNG_PCIE_DEVICE_ID 0xa575
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#define SAMSUNG_PCIE_CH_NUM 1
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#elif defined(CONFIG_SOC_EXYNOS8890)
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#define SAMSUNG_PCIE_DEVICE_ID 0xa544
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#define SAMSUNG_PCIE_CH_NUM 0
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#else
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#error "Not supported platform"
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#endif
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#ifdef CONFIG_MACH_UNIVERSAL5433
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extern int exynos_pcie_pm_suspend(void);
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extern int exynos_pcie_pm_resume(void);
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#else
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extern int exynos_pcie_pm_suspend(int ch_num);
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extern int exynos_pcie_pm_resume(int ch_num);
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#endif /* CONFIG_MACH_UNIVERSAL5433 */
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#endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
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extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
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#endif /* dhd_pcie_h */
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