/*
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* Copyright (c) 2018, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "port.h"
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/* speed in units of 1Mb */
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static const u32 mlx5e_link_speed[MLX5E_LINK_MODES_NUMBER] = {
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[MLX5E_1000BASE_CX_SGMII] = 1000,
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[MLX5E_1000BASE_KX] = 1000,
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[MLX5E_10GBASE_CX4] = 10000,
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[MLX5E_10GBASE_KX4] = 10000,
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[MLX5E_10GBASE_KR] = 10000,
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[MLX5E_20GBASE_KR2] = 20000,
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[MLX5E_40GBASE_CR4] = 40000,
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[MLX5E_40GBASE_KR4] = 40000,
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[MLX5E_56GBASE_R4] = 56000,
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[MLX5E_10GBASE_CR] = 10000,
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[MLX5E_10GBASE_SR] = 10000,
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[MLX5E_10GBASE_ER] = 10000,
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[MLX5E_40GBASE_SR4] = 40000,
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[MLX5E_40GBASE_LR4] = 40000,
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[MLX5E_50GBASE_SR2] = 50000,
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[MLX5E_100GBASE_CR4] = 100000,
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[MLX5E_100GBASE_SR4] = 100000,
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[MLX5E_100GBASE_KR4] = 100000,
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[MLX5E_100GBASE_LR4] = 100000,
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[MLX5E_100BASE_TX] = 100,
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[MLX5E_1000BASE_T] = 1000,
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[MLX5E_10GBASE_T] = 10000,
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[MLX5E_25GBASE_CR] = 25000,
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[MLX5E_25GBASE_KR] = 25000,
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[MLX5E_25GBASE_SR] = 25000,
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[MLX5E_50GBASE_CR2] = 50000,
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[MLX5E_50GBASE_KR2] = 50000,
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};
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u32 mlx5e_port_ptys2speed(u32 eth_proto_oper)
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{
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unsigned long temp = eth_proto_oper;
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u32 speed = 0;
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int i;
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i = find_first_bit(&temp, MLX5E_LINK_MODES_NUMBER);
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if (i < MLX5E_LINK_MODES_NUMBER)
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speed = mlx5e_link_speed[i];
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return speed;
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}
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int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
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{
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u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
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u32 eth_proto_oper;
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int err;
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err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
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if (err)
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return err;
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eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
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*speed = mlx5e_port_ptys2speed(eth_proto_oper);
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if (!(*speed))
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err = -EINVAL;
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return err;
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}
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int mlx5e_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
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{
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u32 max_speed = 0;
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u32 proto_cap;
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int err;
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int i;
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err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
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if (err)
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return err;
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for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
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if (proto_cap & MLX5E_PROT_MASK(i))
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max_speed = max(max_speed, mlx5e_link_speed[i]);
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*speed = max_speed;
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return 0;
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}
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u32 mlx5e_port_speed2linkmodes(u32 speed)
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{
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u32 link_modes = 0;
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int i;
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for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
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if (mlx5e_link_speed[i] == speed)
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link_modes |= MLX5E_PROT_MASK(i);
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}
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return link_modes;
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}
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int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out)
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{
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int sz = MLX5_ST_SZ_BYTES(pbmc_reg);
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void *in;
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int err;
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in = kzalloc(sz, GFP_KERNEL);
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if (!in)
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return -ENOMEM;
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MLX5_SET(pbmc_reg, in, local_port, 1);
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err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 0);
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kfree(in);
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return err;
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}
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int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in)
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{
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int sz = MLX5_ST_SZ_BYTES(pbmc_reg);
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void *out;
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int err;
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out = kzalloc(sz, GFP_KERNEL);
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if (!out)
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return -ENOMEM;
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MLX5_SET(pbmc_reg, in, local_port, 1);
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err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 1);
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kfree(out);
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return err;
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}
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/* buffer[i]: buffer that priority i mapped to */
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int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
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{
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int sz = MLX5_ST_SZ_BYTES(pptb_reg);
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u32 prio_x_buff;
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void *out;
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void *in;
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int prio;
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int err;
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in = kzalloc(sz, GFP_KERNEL);
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out = kzalloc(sz, GFP_KERNEL);
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if (!in || !out) {
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err = -ENOMEM;
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goto out;
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}
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MLX5_SET(pptb_reg, in, local_port, 1);
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err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
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if (err)
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goto out;
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prio_x_buff = MLX5_GET(pptb_reg, out, prio_x_buff);
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for (prio = 0; prio < 8; prio++) {
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buffer[prio] = (u8)(prio_x_buff >> (4 * prio)) & 0xF;
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mlx5_core_dbg(mdev, "prio %d, buffer %d\n", prio, buffer[prio]);
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}
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out:
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kfree(in);
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kfree(out);
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return err;
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}
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int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
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{
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int sz = MLX5_ST_SZ_BYTES(pptb_reg);
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u32 prio_x_buff;
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void *out;
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void *in;
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int prio;
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int err;
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in = kzalloc(sz, GFP_KERNEL);
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out = kzalloc(sz, GFP_KERNEL);
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if (!in || !out) {
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err = -ENOMEM;
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goto out;
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}
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/* First query the pptb register */
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MLX5_SET(pptb_reg, in, local_port, 1);
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err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
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if (err)
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goto out;
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memcpy(in, out, sz);
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MLX5_SET(pptb_reg, in, local_port, 1);
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/* Update the pm and prio_x_buff */
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MLX5_SET(pptb_reg, in, pm, 0xFF);
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prio_x_buff = 0;
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for (prio = 0; prio < 8; prio++)
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prio_x_buff |= (buffer[prio] << (4 * prio));
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MLX5_SET(pptb_reg, in, prio_x_buff, prio_x_buff);
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err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 1);
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out:
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kfree(in);
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kfree(out);
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return err;
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}
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