/*
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* aQuantia Corporation Network Driver
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* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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/* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
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* Atlantic hardware abstraction layer.
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*/
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#include "../aq_hw.h"
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#include "../aq_hw_utils.h"
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#include "../aq_pci_func.h"
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#include "../aq_ring.h"
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#include "../aq_vec.h"
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#include "hw_atl_utils.h"
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#include "hw_atl_llh.h"
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#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
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#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
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#define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
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#define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
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#define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
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#define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
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#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
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static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
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static int aq_fw2x_set_state(struct aq_hw_s *self,
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enum hal_atl_utils_fw_state_e state);
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static int aq_fw2x_init(struct aq_hw_s *self)
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{
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int err = 0;
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/* check 10 times by 1ms */
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AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
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aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
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1000U, 10U);
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AQ_HW_WAIT_FOR(0U != (self->rpc_addr =
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aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)),
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1000U, 100U);
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return err;
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}
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static int aq_fw2x_deinit(struct aq_hw_s *self)
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{
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int err = aq_fw2x_set_link_speed(self, 0);
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if (!err)
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err = aq_fw2x_set_state(self, MPI_DEINIT);
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return err;
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}
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static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
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{
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enum hw_atl_fw2x_rate rate = 0;
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if (speed & AQ_NIC_RATE_10G)
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rate |= FW2X_RATE_10G;
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if (speed & AQ_NIC_RATE_5G)
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rate |= FW2X_RATE_5G;
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if (speed & AQ_NIC_RATE_5GSR)
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rate |= FW2X_RATE_5G;
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if (speed & AQ_NIC_RATE_2GS)
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rate |= FW2X_RATE_2G5;
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if (speed & AQ_NIC_RATE_1G)
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rate |= FW2X_RATE_1G;
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if (speed & AQ_NIC_RATE_100M)
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rate |= FW2X_RATE_100M;
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return rate;
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}
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static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
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{
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u32 val = link_speed_mask_2fw2x_ratemask(speed);
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
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return 0;
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}
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static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
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{
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if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
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*mpi_state |= BIT(CAPS_HI_PAUSE);
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else
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*mpi_state &= ~BIT(CAPS_HI_PAUSE);
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if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
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*mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
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else
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*mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
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}
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static int aq_fw2x_set_state(struct aq_hw_s *self,
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enum hal_atl_utils_fw_state_e state)
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{
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u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
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switch (state) {
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case MPI_INIT:
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mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
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aq_fw2x_set_mpi_flow_control(self, &mpi_state);
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break;
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case MPI_DEINIT:
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mpi_state |= BIT(CAPS_HI_LINK_DROP);
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break;
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case MPI_RESET:
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case MPI_POWER:
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/* No actions */
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break;
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}
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
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return 0;
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}
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static int aq_fw2x_update_link_status(struct aq_hw_s *self)
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{
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u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
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u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
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FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
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struct aq_hw_link_status_s *link_status = &self->aq_link_status;
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if (speed) {
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if (speed & FW2X_RATE_10G)
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link_status->mbps = 10000;
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else if (speed & FW2X_RATE_5G)
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link_status->mbps = 5000;
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else if (speed & FW2X_RATE_2G5)
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link_status->mbps = 2500;
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else if (speed & FW2X_RATE_1G)
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link_status->mbps = 1000;
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else if (speed & FW2X_RATE_100M)
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link_status->mbps = 100;
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else
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link_status->mbps = 10000;
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} else {
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link_status->mbps = 0;
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}
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return 0;
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}
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static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
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{
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int err = 0;
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u32 h = 0U;
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u32 l = 0U;
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u32 mac_addr[2] = { 0 };
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u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
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if (efuse_addr != 0) {
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err = hw_atl_utils_fw_downld_dwords(self,
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efuse_addr + (40U * 4U),
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mac_addr,
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ARRAY_SIZE(mac_addr));
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if (err)
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return err;
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mac_addr[0] = __swab32(mac_addr[0]);
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mac_addr[1] = __swab32(mac_addr[1]);
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}
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ether_addr_copy(mac, (u8 *)mac_addr);
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if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
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unsigned int rnd = 0;
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get_random_bytes(&rnd, sizeof(unsigned int));
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l = 0xE3000000U
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| (0xFFFFU & rnd)
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| (0x00 << 16);
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h = 0x8001300EU;
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mac[5] = (u8)(0xFFU & l);
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l >>= 8;
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mac[4] = (u8)(0xFFU & l);
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l >>= 8;
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mac[3] = (u8)(0xFFU & l);
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l >>= 8;
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mac[2] = (u8)(0xFFU & l);
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mac[1] = (u8)(0xFFU & h);
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h >>= 8;
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mac[0] = (u8)(0xFFU & h);
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}
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return err;
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}
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static int aq_fw2x_update_stats(struct aq_hw_s *self)
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{
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int err = 0;
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u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
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u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
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/* Toggle statistics bit for FW to update */
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mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
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/* Wait FW to report back */
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AQ_HW_WAIT_FOR(orig_stats_val !=
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(aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
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BIT(CAPS_HI_STATISTICS)),
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1U, 10000U);
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if (err)
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return err;
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return hw_atl_utils_update_stats(self);
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}
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static int aq_fw2x_renegotiate(struct aq_hw_s *self)
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{
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u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
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mpi_opts |= BIT(CTRL_FORCE_RECONNECT);
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
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return 0;
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}
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static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
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{
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u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
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aq_fw2x_set_mpi_flow_control(self, &mpi_state);
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
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return 0;
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}
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const struct aq_fw_ops aq_fw_2x_ops = {
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.init = aq_fw2x_init,
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.deinit = aq_fw2x_deinit,
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.reset = NULL,
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.renegotiate = aq_fw2x_renegotiate,
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.get_mac_permanent = aq_fw2x_get_mac_permanent,
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.set_link_speed = aq_fw2x_set_link_speed,
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.set_state = aq_fw2x_set_state,
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.update_link_status = aq_fw2x_update_link_status,
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.update_stats = aq_fw2x_update_stats,
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.set_flow_control = aq_fw2x_set_flow_control,
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};
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