/*
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* Copyright 2015 Martin Peres
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Martin Peres
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*/
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#include <subdev/bios.h>
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#include <subdev/bios/bit.h>
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#include <subdev/bios/extdev.h>
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#include <subdev/bios/iccsense.h>
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static u32
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nvbios_iccsense_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt,
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u8 *len)
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{
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struct bit_entry bit_P;
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u32 iccsense;
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if (bit_entry(bios, 'P', &bit_P) || bit_P.version != 2 ||
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bit_P.length < 0x2c)
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return 0;
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iccsense = nvbios_rd32(bios, bit_P.offset + 0x28);
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if (!iccsense)
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return 0;
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*ver = nvbios_rd08(bios, iccsense + 0);
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switch (*ver) {
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case 0x10:
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case 0x20:
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*hdr = nvbios_rd08(bios, iccsense + 1);
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*len = nvbios_rd08(bios, iccsense + 2);
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*cnt = nvbios_rd08(bios, iccsense + 3);
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return iccsense;
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default:
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break;
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}
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return 0;
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}
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int
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nvbios_iccsense_parse(struct nvkm_bios *bios, struct nvbios_iccsense *iccsense)
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{
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struct nvkm_subdev *subdev = &bios->subdev;
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u8 ver, hdr, cnt, len, i;
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u32 table, entry;
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table = nvbios_iccsense_table(bios, &ver, &hdr, &cnt, &len);
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if (!table || !cnt)
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return -EINVAL;
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if (ver != 0x10 && ver != 0x20) {
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nvkm_error(subdev, "ICCSENSE version 0x%02x unknown\n", ver);
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return -EINVAL;
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}
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iccsense->nr_entry = cnt;
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iccsense->rail = kmalloc_array(cnt, sizeof(struct pwr_rail_t),
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GFP_KERNEL);
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if (!iccsense->rail)
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return -ENOMEM;
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for (i = 0; i < cnt; ++i) {
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struct nvbios_extdev_func extdev;
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struct pwr_rail_t *rail = &iccsense->rail[i];
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u8 res_start = 0;
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int r;
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entry = table + hdr + i * len;
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switch(ver) {
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case 0x10:
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if ((nvbios_rd08(bios, entry + 0x1) & 0xf8) == 0xf8)
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rail->mode = 1;
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else
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rail->mode = 0;
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rail->extdev_id = nvbios_rd08(bios, entry + 0x2);
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res_start = 0x3;
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break;
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case 0x20:
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rail->mode = nvbios_rd08(bios, entry);
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rail->extdev_id = nvbios_rd08(bios, entry + 0x1);
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res_start = 0x5;
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break;
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}
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if (nvbios_extdev_parse(bios, rail->extdev_id, &extdev))
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continue;
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switch (extdev.type) {
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case NVBIOS_EXTDEV_INA209:
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case NVBIOS_EXTDEV_INA219:
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rail->resistor_count = 1;
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break;
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case NVBIOS_EXTDEV_INA3221:
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rail->resistor_count = 3;
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break;
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default:
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rail->resistor_count = 0;
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break;
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}
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for (r = 0; r < rail->resistor_count; ++r) {
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rail->resistors[r].mohm = nvbios_rd08(bios, entry + res_start + r * 2);
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rail->resistors[r].enabled = !(nvbios_rd08(bios, entry + res_start + r * 2 + 1) & 0x40);
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}
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rail->config = nvbios_rd16(bios, entry + res_start + rail->resistor_count * 2);
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}
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return 0;
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}
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