/*
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*
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* Copyright (C) 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef OSS_1_0_D_H
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#define OSS_1_0_D_H
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#define ixCLIENT0_BM 0x0220
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#define ixCLIENT0_CD0 0x0210
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#define ixCLIENT0_CD1 0x0214
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#define ixCLIENT0_CD2 0x0218
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#define ixCLIENT0_CD3 0x021C
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#define ixCLIENT0_CK0 0x0200
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#define ixCLIENT0_CK1 0x0204
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#define ixCLIENT0_CK2 0x0208
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#define ixCLIENT0_CK3 0x020C
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#define ixCLIENT0_K0 0x01F0
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#define ixCLIENT0_K1 0x01F4
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#define ixCLIENT0_K2 0x01F8
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#define ixCLIENT0_K3 0x01FC
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#define ixCLIENT0_OFFSET 0x0224
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#define ixCLIENT0_OFFSET_HI 0x0290
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#define ixCLIENT0_STATUS 0x0228
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#define ixCLIENT1_BM 0x025C
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#define ixCLIENT1_CD0 0x024C
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#define ixCLIENT1_CD1 0x0250
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#define ixCLIENT1_CD2 0x0254
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#define ixCLIENT1_CD3 0x0258
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#define ixCLIENT1_CK0 0x023C
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#define ixCLIENT1_CK1 0x0240
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#define ixCLIENT1_CK2 0x0244
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#define ixCLIENT1_CK3 0x0248
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#define ixCLIENT1_K0 0x022C
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#define ixCLIENT1_K1 0x0230
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#define ixCLIENT1_K2 0x0234
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#define ixCLIENT1_K3 0x0238
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#define ixCLIENT1_OFFSET 0x0260
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#define ixCLIENT1_OFFSET_HI 0x0294
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#define ixCLIENT1_PORT_STATUS 0x0264
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#define ixCLIENT2_BM 0x01E4
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#define ixCLIENT2_CD0 0x01D4
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#define ixCLIENT2_CD1 0x01D8
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#define ixCLIENT2_CD2 0x01DC
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#define ixCLIENT2_CD3 0x01E0
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#define ixCLIENT2_CK0 0x01C4
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#define ixCLIENT2_CK1 0x01C8
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#define ixCLIENT2_CK2 0x01CC
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#define ixCLIENT2_CK3 0x01D0
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#define ixCLIENT2_K0 0x01B4
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#define ixCLIENT2_K1 0x01B8
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#define ixCLIENT2_K2 0x01BC
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#define ixCLIENT2_K3 0x01C0
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#define ixCLIENT2_OFFSET 0x01E8
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#define ixCLIENT2_OFFSET_HI 0x0298
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#define ixCLIENT2_STATUS 0x01EC
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#define ixCLIENT3_BM 0x02D4
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#define ixCLIENT3_CD0 0x02C4
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#define ixCLIENT3_CD1 0x02C8
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#define ixCLIENT3_CD2 0x02CC
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#define ixCLIENT3_CD3 0x02D0
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#define ixCLIENT3_CK0 0x02B4
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#define ixCLIENT3_CK1 0x02B8
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#define ixCLIENT3_CK2 0x02BC
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#define ixCLIENT3_CK3 0x02C0
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#define ixCLIENT3_K0 0x02A4
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#define ixCLIENT3_K1 0x02A8
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#define ixCLIENT3_K2 0x02AC
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#define ixCLIENT3_K3 0x02B0
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#define ixCLIENT3_OFFSET 0x02D8
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#define ixCLIENT3_OFFSET_HI 0x02A0
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#define ixCLIENT3_STATUS 0x02DC
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#define ixDH_TEST 0x0000
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#define ixEXP0 0x0034
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#define ixEXP1 0x0038
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#define ixEXP2 0x003C
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#define ixEXP3 0x0040
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#define ixEXP4 0x0044
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#define ixEXP5 0x0048
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#define ixEXP6 0x004C
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#define ixEXP7 0x0050
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#define ixHFS_SEED0 0x0278
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#define ixHFS_SEED1 0x027C
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#define ixHFS_SEED2 0x0280
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#define ixHFS_SEED3 0x0284
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#define ixKEFUSE0 0x0268
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#define ixKEFUSE1 0x026C
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#define ixKEFUSE2 0x0270
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#define ixKEFUSE3 0x0274
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#define ixKHFS0 0x0004
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#define ixKHFS1 0x0008
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#define ixKHFS2 0x000C
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#define ixKHFS3 0x0010
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#define ixKSESSION0 0x0014
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#define ixKSESSION1 0x0018
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#define ixKSESSION2 0x001C
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#define ixKSESSION3 0x0020
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#define ixKSIG0 0x0024
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#define ixKSIG1 0x0028
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#define ixKSIG2 0x002C
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#define ixKSIG3 0x0030
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#define ixLX0 0x0054
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#define ixLX1 0x0058
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#define ixLX2 0x005C
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#define ixLX3 0x0060
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#define ixRINGOSC_MASK 0x0288
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#define ixSPU_PORT_STATUS 0x029C
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#define mmCC_DRM_ID_STRAPS 0x1559
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#define mmCC_SYS_RB_BACKEND_DISABLE 0x03A0
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#define mmCC_SYS_RB_REDUNDANCY 0x039F
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#define mmCGTT_DRM_CLK_CTRL0 0x1579
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#define mmCP_CONFIG 0x0F92
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#define mmDC_TEST_DEBUG_DATA 0x157D
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#define mmDC_TEST_DEBUG_INDEX 0x157C
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#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x03A1
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#define mmHDP_ADDR_CONFIG 0x0BD2
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#define mmHDP_DEBUG0 0x0BCC
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#define mmHDP_DEBUG1 0x0BCD
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#define mmHDP_HOST_PATH_CNTL 0x0B00
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#define mmHDP_LAST_SURFACE_HIT 0x0BCE
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#define mmHDP_MEMIO_ADDR 0x0BF7
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#define mmHDP_MEMIO_CNTL 0x0BF6
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#define mmHDP_MEMIO_RD_DATA 0x0BFA
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#define mmHDP_MEMIO_STATUS 0x0BF8
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#define mmHDP_MEMIO_WR_DATA 0x0BF9
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#define mmHDP_MEM_POWER_LS 0x0BD4
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#define mmHDP_MISC_CNTL 0x0BD3
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#define mmHDP_NONSURFACE_BASE 0x0B01
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#define mmHDP_NONSURFACE_INFO 0x0B02
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#define mmHDP_NONSURFACE_PREFETCH 0x0BD5
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#define mmHDP_NONSURFACE_SIZE 0x0B03
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#define mmHDP_NONSURF_FLAGS 0x0BC9
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#define mmHDP_NONSURF_FLAGS_CLR 0x0BCA
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#define mmHDP_OUTSTANDING_REQ 0x0BD1
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#define mmHDP_SC_MULTI_CHIP_CNTL 0x0BD0
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#define mmHDP_SW_SEMAPHORE 0x0BCB
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#define mmHDP_TILING_CONFIG 0x0BCF
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#define mmHDP_XDP_BARS_ADDR_39_36 0x0C44
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#define mmHDP_XDP_BUSY_STS 0x0C3E
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#define mmHDP_XDP_CGTT_BLK_CTRL 0x0C33
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#define mmHDP_XDP_CHKN 0x0C40
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#define mmHDP_XDP_D2H_BAR_UPDATE 0x0C02
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#define mmHDP_XDP_D2H_FLUSH 0x0C01
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#define mmHDP_XDP_D2H_RSVD_10 0x0C0A
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#define mmHDP_XDP_D2H_RSVD_11 0x0C0B
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#define mmHDP_XDP_D2H_RSVD_12 0x0C0C
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#define mmHDP_XDP_D2H_RSVD_13 0x0C0D
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#define mmHDP_XDP_D2H_RSVD_14 0x0C0E
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#define mmHDP_XDP_D2H_RSVD_15 0x0C0F
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#define mmHDP_XDP_D2H_RSVD_16 0x0C10
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#define mmHDP_XDP_D2H_RSVD_17 0x0C11
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#define mmHDP_XDP_D2H_RSVD_18 0x0C12
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#define mmHDP_XDP_D2H_RSVD_19 0x0C13
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#define mmHDP_XDP_D2H_RSVD_20 0x0C14
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#define mmHDP_XDP_D2H_RSVD_21 0x0C15
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#define mmHDP_XDP_D2H_RSVD_22 0x0C16
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#define mmHDP_XDP_D2H_RSVD_23 0x0C17
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#define mmHDP_XDP_D2H_RSVD_24 0x0C18
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#define mmHDP_XDP_D2H_RSVD_25 0x0C19
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#define mmHDP_XDP_D2H_RSVD_26 0x0C1A
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#define mmHDP_XDP_D2H_RSVD_27 0x0C1B
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#define mmHDP_XDP_D2H_RSVD_28 0x0C1C
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#define mmHDP_XDP_D2H_RSVD_29 0x0C1D
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#define mmHDP_XDP_D2H_RSVD_30 0x0C1E
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#define mmHDP_XDP_D2H_RSVD_3 0x0C03
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#define mmHDP_XDP_D2H_RSVD_31 0x0C1F
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#define mmHDP_XDP_D2H_RSVD_32 0x0C20
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#define mmHDP_XDP_D2H_RSVD_33 0x0C21
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#define mmHDP_XDP_D2H_RSVD_34 0x0C22
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#define mmHDP_XDP_D2H_RSVD_4 0x0C04
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#define mmHDP_XDP_D2H_RSVD_5 0x0C05
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#define mmHDP_XDP_D2H_RSVD_6 0x0C06
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#define mmHDP_XDP_D2H_RSVD_7 0x0C07
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#define mmHDP_XDP_D2H_RSVD_8 0x0C08
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#define mmHDP_XDP_D2H_RSVD_9 0x0C09
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#define mmHDP_XDP_DBG_ADDR 0x0C41
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#define mmHDP_XDP_DBG_DATA 0x0C42
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#define mmHDP_XDP_DBG_MASK 0x0C43
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#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0C00
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#define mmHDP_XDP_DIRECT2HDP_LAST 0x0C23
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#define mmHDP_XDP_FLUSH_ARMED_STS 0x0C3C
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#define mmHDP_XDP_FLUSH_CNTR0_STS 0x0C3D
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#define mmHDP_XDP_HDP_IPH_CFG 0x0C31
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#define mmHDP_XDP_HDP_MBX_MC_CFG 0x0C2D
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#define mmHDP_XDP_HDP_MC_CFG 0x0C2E
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#define mmHDP_XDP_HST_CFG 0x0C2F
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#define mmHDP_XDP_P2P_BAR0 0x0C34
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#define mmHDP_XDP_P2P_BAR1 0x0C35
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#define mmHDP_XDP_P2P_BAR2 0x0C36
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#define mmHDP_XDP_P2P_BAR3 0x0C37
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#define mmHDP_XDP_P2P_BAR4 0x0C38
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#define mmHDP_XDP_P2P_BAR5 0x0C39
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#define mmHDP_XDP_P2P_BAR6 0x0C3A
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#define mmHDP_XDP_P2P_BAR7 0x0C3B
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#define mmHDP_XDP_P2P_BAR_CFG 0x0C24
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#define mmHDP_XDP_P2P_MBX_ADDR0 0x0C26
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#define mmHDP_XDP_P2P_MBX_ADDR1 0x0C27
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#define mmHDP_XDP_P2P_MBX_ADDR2 0x0C28
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#define mmHDP_XDP_P2P_MBX_ADDR3 0x0C29
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#define mmHDP_XDP_P2P_MBX_ADDR4 0x0C2A
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#define mmHDP_XDP_P2P_MBX_ADDR5 0x0C2B
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#define mmHDP_XDP_P2P_MBX_ADDR6 0x0C2C
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#define mmHDP_XDP_P2P_MBX_OFFSET 0x0C25
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#define mmHDP_XDP_SID_CFG 0x0C30
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#define mmHDP_XDP_SRBM_CFG 0x0C32
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#define mmHDP_XDP_STICKY 0x0C3F
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#define mmIH_ADVFAULT_CNTL 0x0F8C
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#define mmIH_CNTL 0x0F86
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#define mmIH_LEVEL_STATUS 0x0F87
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#define mmIH_PERFCOUNTER0_RESULT 0x0F8A
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#define mmIH_PERFCOUNTER1_RESULT 0x0F8B
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#define mmIH_PERFMON_CNTL 0x0F89
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#define mmIH_RB_BASE 0x0F81
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#define mmIH_RB_CNTL 0x0F80
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#define mmIH_RB_RPTR 0x0F82
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#define mmIH_RB_WPTR 0x0F83
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#define mmIH_RB_WPTR_ADDR_HI 0x0F84
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#define mmIH_RB_WPTR_ADDR_LO 0x0F85
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#define mmIH_STATUS 0x0F88
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#define mmSEM_MAILBOX 0x0F9B
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#define mmSEM_MAILBOX_CLIENTCONFIG 0x0F9A
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#define mmSEM_MAILBOX_CONTROL 0x0F9C
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#define mmSEM_MCIF_CONFIG 0x0F90
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#define mmSRBM_CAM_DATA 0x0397
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#define mmSRBM_CAM_INDEX 0x0396
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#define mmSRBM_CHIP_REVISION 0x039B
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#define mmSRBM_CNTL 0x0390
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#define mmSRBM_DEBUG 0x03A4
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#define mmSRBM_DEBUG_CNTL 0x0399
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#define mmSRBM_DEBUG_DATA 0x039A
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#define mmSRBM_DEBUG_SNAPSHOT 0x03A5
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#define mmSRBM_GFX_CNTL 0x0391
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#define mmSRBM_INT_ACK 0x03AA
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#define mmSRBM_INT_CNTL 0x03A8
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#define mmSRBM_INT_STATUS 0x03A9
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#define mmSRBM_MC_CLKEN_CNTL 0x03B3
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#define mmSRBM_PERFCOUNTER0_HI 0x0704
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#define mmSRBM_PERFCOUNTER0_LO 0x0703
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#define mmSRBM_PERFCOUNTER0_SELECT 0x0701
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#define mmSRBM_PERFCOUNTER1_HI 0x0706
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#define mmSRBM_PERFCOUNTER1_LO 0x0705
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#define mmSRBM_PERFCOUNTER1_SELECT 0x0702
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#define mmSRBM_PERFMON_CNTL 0x0700
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#define mmSRBM_READ_ERROR 0x03A6
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#define mmSRBM_SOFT_RESET 0x0398
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#define mmSRBM_STATUS 0x0394
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#define mmSRBM_STATUS2 0x0393
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#define mmSRBM_SYS_CLKEN_CNTL 0x03B4
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#define mmSRBM_UVD_CLKEN_CNTL 0x03B6
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#define mmSRBM_VCE_CLKEN_CNTL 0x03B5
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#define mmUVD_CONFIG 0x0F98
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#define mmVCE_CONFIG 0x0F94
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#define mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0x03F8
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/* from the old sid.h */
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#define mmDMA_TILING_CONFIG 0x342E
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#endif
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