/* Copyright 2015 Advanced Micro Devices, Inc. */
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#include "dm_services.h"
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#include "dc.h"
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#include "inc/core_types.h"
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#include "include/ddc_service_types.h"
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#include "include/i2caux_interface.h"
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#include "link_hwss.h"
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#include "hw_sequencer.h"
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#include "dc_link_dp.h"
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#include "dc_link_ddc.h"
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#include "dm_helpers.h"
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#include "dpcd_defs.h"
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enum dc_status core_link_read_dpcd(
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struct dc_link *link,
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uint32_t address,
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uint8_t *data,
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uint32_t size)
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{
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if (!dm_helpers_dp_read_dpcd(link->ctx,
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link,
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address, data, size))
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return DC_ERROR_UNEXPECTED;
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return DC_OK;
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}
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enum dc_status core_link_write_dpcd(
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struct dc_link *link,
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uint32_t address,
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const uint8_t *data,
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uint32_t size)
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{
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if (!dm_helpers_dp_write_dpcd(link->ctx,
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link,
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address, data, size))
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return DC_ERROR_UNEXPECTED;
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return DC_OK;
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}
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void dp_receiver_power_ctrl(struct dc_link *link, bool on)
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{
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uint8_t state;
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state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3;
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core_link_write_dpcd(link, DP_SET_POWER, &state,
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sizeof(state));
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}
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void dp_enable_link_phy(
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struct dc_link *link,
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enum signal_type signal,
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enum clock_source_id clock_source,
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const struct dc_link_settings *link_settings)
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{
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struct link_encoder *link_enc = link->link_enc;
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struct pipe_ctx *pipes =
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link->dc->current_state->res_ctx.pipe_ctx;
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struct clock_source *dp_cs =
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link->dc->res_pool->dp_clock_source;
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unsigned int i;
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/* If the current pixel clock source is not DTO(happens after
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* switching from HDMI passive dongle to DP on the same connector),
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* switch the pixel clock source to DTO.
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*/
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for (i = 0; i < MAX_PIPES; i++) {
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if (pipes[i].stream != NULL &&
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pipes[i].stream->sink != NULL &&
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pipes[i].stream->sink->link == link) {
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if (pipes[i].clock_source != NULL &&
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pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
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pipes[i].clock_source = dp_cs;
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pipes[i].stream_res.pix_clk_params.requested_pix_clk =
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pipes[i].stream->timing.pix_clk_khz;
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pipes[i].clock_source->funcs->program_pix_clk(
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pipes[i].clock_source,
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&pipes[i].stream_res.pix_clk_params,
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&pipes[i].pll_settings);
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}
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}
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}
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if (dc_is_dp_sst_signal(signal)) {
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link_enc->funcs->enable_dp_output(
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link_enc,
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link_settings,
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clock_source);
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} else {
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link_enc->funcs->enable_dp_mst_output(
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link_enc,
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link_settings,
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clock_source);
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}
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dp_receiver_power_ctrl(link, true);
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}
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bool edp_receiver_ready_T9(struct dc_link *link)
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{
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unsigned int tries = 0;
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unsigned char sinkstatus = 0;
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unsigned char edpRev = 0;
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enum dc_status result = DC_OK;
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result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
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if (edpRev < DP_EDP_12)
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return true;
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/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
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do {
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sinkstatus = 1;
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result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
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if (sinkstatus == 0)
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break;
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if (result != DC_OK)
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break;
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udelay(100); //MAx T9
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} while (++tries < 50);
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return result;
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}
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bool edp_receiver_ready_T7(struct dc_link *link)
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{
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unsigned int tries = 0;
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unsigned char sinkstatus = 0;
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unsigned char edpRev = 0;
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enum dc_status result = DC_OK;
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result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
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if (result == DC_OK && edpRev < DP_EDP_12)
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return true;
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/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
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do {
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sinkstatus = 0;
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result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
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if (sinkstatus == 1)
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break;
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if (result != DC_OK)
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break;
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udelay(25); //MAx T7 is 50ms
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} while (++tries < 300);
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return result;
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}
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void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
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{
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if (!link->wa_flags.dp_keep_receiver_powered)
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dp_receiver_power_ctrl(link, false);
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if (signal == SIGNAL_TYPE_EDP) {
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link->link_enc->funcs->disable_output(link->link_enc, signal);
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link->dc->hwss.edp_power_control(link, false);
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} else
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link->link_enc->funcs->disable_output(link->link_enc, signal);
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/* Clear current link setting.*/
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memset(&link->cur_link_settings, 0,
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sizeof(link->cur_link_settings));
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}
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void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
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{
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/* MST disable link only when no stream use the link */
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if (link->mst_stream_alloc_table.stream_count > 0)
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return;
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dp_disable_link_phy(link, signal);
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/* set the sink to SST mode after disabling the link */
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dp_enable_mst_on_sink(link, false);
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}
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bool dp_set_hw_training_pattern(
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struct dc_link *link,
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enum hw_dp_training_pattern pattern)
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{
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enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
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switch (pattern) {
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case HW_DP_TRAINING_PATTERN_1:
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test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
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break;
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case HW_DP_TRAINING_PATTERN_2:
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test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
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break;
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case HW_DP_TRAINING_PATTERN_3:
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test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
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break;
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case HW_DP_TRAINING_PATTERN_4:
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test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
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break;
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default:
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break;
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}
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dp_set_hw_test_pattern(link, test_pattern, NULL, 0);
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return true;
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}
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void dp_set_hw_lane_settings(
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struct dc_link *link,
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const struct link_training_settings *link_settings)
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{
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struct link_encoder *encoder = link->link_enc;
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/* call Encoder to set lane settings */
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encoder->funcs->dp_set_lane_settings(encoder, link_settings);
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}
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enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
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{
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/* We need to explicitly check that connector
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* is not DP. Some Travis_VGA get reported
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* by video bios as DP.
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*/
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if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
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switch (link->dpcd_caps.branch_dev_id) {
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case DP_BRANCH_DEVICE_ID_2:
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if (strncmp(
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link->dpcd_caps.branch_dev_name,
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DP_VGA_LVDS_CONVERTER_ID_2,
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sizeof(
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link->dpcd_caps.
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branch_dev_name)) == 0) {
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return DP_PANEL_MODE_SPECIAL;
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}
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break;
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case DP_BRANCH_DEVICE_ID_3:
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if (strncmp(link->dpcd_caps.branch_dev_name,
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DP_VGA_LVDS_CONVERTER_ID_3,
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sizeof(
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link->dpcd_caps.
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branch_dev_name)) == 0) {
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return DP_PANEL_MODE_SPECIAL;
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}
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break;
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default:
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break;
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}
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}
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if (link->dpcd_caps.panel_mode_edp) {
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return DP_PANEL_MODE_EDP;
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}
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return DP_PANEL_MODE_DEFAULT;
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}
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void dp_set_hw_test_pattern(
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struct dc_link *link,
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enum dp_test_pattern test_pattern,
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uint8_t *custom_pattern,
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uint32_t custom_pattern_size)
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{
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struct encoder_set_dp_phy_pattern_param pattern_param = {0};
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struct link_encoder *encoder = link->link_enc;
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pattern_param.dp_phy_pattern = test_pattern;
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pattern_param.custom_pattern = custom_pattern;
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pattern_param.custom_pattern_size = custom_pattern_size;
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pattern_param.dp_panel_mode = dp_get_panel_mode(link);
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encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
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}
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void dp_retrain_link_dp_test(struct dc_link *link,
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struct dc_link_settings *link_setting,
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bool skip_video_pattern)
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{
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struct pipe_ctx *pipes =
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&link->dc->current_state->res_ctx.pipe_ctx[0];
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unsigned int i;
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for (i = 0; i < MAX_PIPES; i++) {
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if (pipes[i].stream != NULL &&
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!pipes[i].top_pipe &&
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pipes[i].stream->sink != NULL &&
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pipes[i].stream->sink->link != NULL &&
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pipes[i].stream_res.stream_enc != NULL &&
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pipes[i].stream->sink->link == link) {
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udelay(100);
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pipes[i].stream_res.stream_enc->funcs->dp_blank(
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pipes[i].stream_res.stream_enc);
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/* disable any test pattern that might be active */
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dp_set_hw_test_pattern(link,
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DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
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dp_receiver_power_ctrl(link, false);
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link->dc->hwss.disable_stream(&pipes[i], KEEP_ACQUIRED_RESOURCE);
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link->link_enc->funcs->disable_output(
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link->link_enc,
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SIGNAL_TYPE_DISPLAY_PORT);
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/* Clear current link setting. */
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memset(&link->cur_link_settings, 0,
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sizeof(link->cur_link_settings));
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link->link_enc->funcs->enable_dp_output(
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link->link_enc,
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link_setting,
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pipes[i].clock_source->id);
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dp_receiver_power_ctrl(link, true);
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perform_link_training_with_retries(
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link,
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link_setting,
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skip_video_pattern,
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LINK_TRAINING_ATTEMPTS);
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link->cur_link_settings = *link_setting;
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link->dc->hwss.enable_stream(&pipes[i]);
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link->dc->hwss.unblank_stream(&pipes[i],
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link_setting);
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if (pipes[i].stream_res.audio) {
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/* notify audio driver for
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* audio modes of monitor */
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pipes[i].stream_res.audio->funcs->az_enable(
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pipes[i].stream_res.audio);
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/* un-mute audio */
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/* TODO: audio should be per stream rather than
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* per link */
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pipes[i].stream_res.stream_enc->funcs->
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audio_mute_control(
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pipes[i].stream_res.stream_enc, false);
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}
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}
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}
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}
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