/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2017 Cavium, Inc.
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*/
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/*
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We install this program at the bootvector:
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------------------------------------
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.set noreorder
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.set nomacro
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.set noat
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reset_vector:
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dmtc0 $k0, $31, 0 # Save $k0 to DESAVE
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dmtc0 $k1, $31, 3 # Save $k1 to KScratch2
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mfc0 $k0, $12, 0 # Status
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mfc0 $k1, $15, 1 # Ebase
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ori $k0, 0x84 # Enable 64-bit addressing, set
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# ERL (should already be set)
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andi $k1, 0x3ff # mask out core ID
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mtc0 $k0, $12, 0 # Status
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sll $k1, 5
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lui $k0, 0xbfc0
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cache 17, 0($0) # Core-14345, clear L1 Dcache virtual
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# tags if the core hit an NMI
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ld $k0, 0x78($k0) # k0 <- (bfc00078) pointer to the reset vector
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synci 0($0) # Invalidate ICache to get coherent
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# view of target code.
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daddu $k0, $k0, $k1
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nop
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ld $k0, 0($k0) # k0 <- core specific target address
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dmfc0 $k1, $31, 3 # Restore $k1 from KScratch2
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beqz $k0, wait_loop # Spin in wait loop
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nop
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jr $k0
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nop
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nop # NOPs needed here to fill delay slots
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nop # on endian reversal of previous instructions
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wait_loop:
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wait
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nop
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b wait_loop
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nop
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nop
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nop
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------------------------------------
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0000000000000000 <reset_vector>:
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0: 40baf800 dmtc0 k0,c0_desave
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4: 40bbf803 dmtc0 k1,c0_kscratch2
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8: 401a6000 mfc0 k0,c0_status
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c: 401b7801 mfc0 k1,c0_ebase
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10: 375a0084 ori k0,k0,0x84
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14: 337b03ff andi k1,k1,0x3ff
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18: 409a6000 mtc0 k0,c0_status
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1c: 001bd940 sll k1,k1,0x5
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20: 3c1abfc0 lui k0,0xbfc0
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24: bc110000 cache 0x11,0(zero)
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28: df5a0078 ld k0,120(k0)
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2c: 041f0000 synci 0(zero)
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30: 035bd02d daddu k0,k0,k1
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34: 00000000 nop
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38: df5a0000 ld k0,0(k0)
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3c: 403bf803 dmfc0 k1,c0_kscratch2
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40: 13400005 beqz k0,58 <wait_loop>
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44: 00000000 nop
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48: 03400008 jr k0
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4c: 00000000 nop
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50: 00000000 nop
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54: 00000000 nop
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0000000000000058 <wait_loop>:
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58: 42000020 wait
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5c: 00000000 nop
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60: 1000fffd b 58 <wait_loop>
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64: 00000000 nop
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68: 00000000 nop
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6c: 00000000 nop
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*/
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#include <asm/octeon/cvmx-boot-vector.h>
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static unsigned long long _cvmx_bootvector_data[16] = {
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0x40baf80040bbf803ull, /* patch low order 8-bits if no KScratch*/
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0x401a6000401b7801ull,
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0x375a0084337b03ffull,
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0x409a6000001bd940ull,
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0x3c1abfc0bc110000ull,
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0xdf5a0078041f0000ull,
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0x035bd02d00000000ull,
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0xdf5a0000403bf803ull, /* patch low order 8-bits if no KScratch*/
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0x1340000500000000ull,
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0x0340000800000000ull,
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0x0000000000000000ull,
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0x4200002000000000ull,
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0x1000fffd00000000ull,
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0x0000000000000000ull,
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OCTEON_BOOT_MOVEABLE_MAGIC1,
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0 /* To be filled in with address of vector block*/
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};
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/* 2^10 CPUs */
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#define VECTOR_TABLE_SIZE (1024 * sizeof(struct cvmx_boot_vector_element))
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static void cvmx_boot_vector_init(void *mem)
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{
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uint64_t kseg0_mem;
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int i;
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memset(mem, 0, VECTOR_TABLE_SIZE);
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kseg0_mem = cvmx_ptr_to_phys(mem) | 0x8000000000000000ull;
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for (i = 0; i < 15; i++) {
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uint64_t v = _cvmx_bootvector_data[i];
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if (OCTEON_IS_OCTEON1PLUS() && (i == 0 || i == 7))
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v &= 0xffffffff00000000ull; /* KScratch not availble. */
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v);
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}
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, 15 * 8);
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, kseg0_mem);
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
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}
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/**
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* Get a pointer to the per-core table of reset vector pointers
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*
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*/
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struct cvmx_boot_vector_element *cvmx_boot_vector_get(void)
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{
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struct cvmx_boot_vector_element *ret;
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ret = cvmx_bootmem_alloc_named_range_once(VECTOR_TABLE_SIZE, 0,
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(1ull << 32) - 1, 8, "__boot_vector1__", cvmx_boot_vector_init);
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return ret;
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}
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EXPORT_SYMBOL(cvmx_boot_vector_get);
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