/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MB862XX_H__
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#define __MB862XX_H__
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struct mb862xx_l1_cfg {
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unsigned short sx;
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unsigned short sy;
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unsigned short sw;
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unsigned short sh;
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unsigned short dx;
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unsigned short dy;
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unsigned short dw;
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unsigned short dh;
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int mirror;
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};
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#define MB862XX_BASE 'M'
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#define MB862XX_L1_GET_CFG _IOR(MB862XX_BASE, 0, struct mb862xx_l1_cfg*)
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#define MB862XX_L1_SET_CFG _IOW(MB862XX_BASE, 1, struct mb862xx_l1_cfg*)
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#define MB862XX_L1_ENABLE _IOW(MB862XX_BASE, 2, int)
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#define MB862XX_L1_CAP_CTL _IOW(MB862XX_BASE, 3, int)
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#ifdef __KERNEL__
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#define PCI_VENDOR_ID_FUJITSU_LIMITED 0x10cf
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#define PCI_DEVICE_ID_FUJITSU_CORALP 0x2019
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#define PCI_DEVICE_ID_FUJITSU_CORALPA 0x201e
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#define PCI_DEVICE_ID_FUJITSU_CARMINE 0x202b
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#define GC_MMR_CORALP_EVB_VAL 0x11d7fa13
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enum gdctype {
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BT_NONE,
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BT_LIME,
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BT_MINT,
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BT_CORAL,
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BT_CORALP,
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BT_CARMINE,
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};
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struct mb862xx_gc_mode {
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struct fb_videomode def_mode; /* mode of connected display */
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unsigned int def_bpp; /* default depth */
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unsigned long max_vram; /* connected SDRAM size */
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unsigned long ccf; /* gdc clk */
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unsigned long mmr; /* memory mode for SDRAM */
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};
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/* private data */
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struct mb862xxfb_par {
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struct fb_info *info; /* fb info head */
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struct device *dev;
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struct pci_dev *pdev;
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struct resource *res; /* framebuffer/mmio resource */
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resource_size_t fb_base_phys; /* fb base, 36-bit PPC440EPx */
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resource_size_t mmio_base_phys; /* io base addr */
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void __iomem *fb_base; /* remapped framebuffer */
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void __iomem *mmio_base; /* remapped registers */
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size_t mapped_vram; /* length of remapped vram */
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size_t mmio_len; /* length of register region */
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unsigned long cap_buf; /* capture buffers offset */
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size_t cap_len; /* length of capture buffers */
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void __iomem *host; /* relocatable reg. bases */
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void __iomem *i2c;
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void __iomem *disp;
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void __iomem *disp1;
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void __iomem *cap;
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void __iomem *cap1;
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void __iomem *draw;
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void __iomem *geo;
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void __iomem *pio;
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void __iomem *ctrl;
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void __iomem *dram_ctrl;
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void __iomem *wrback;
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unsigned int irq;
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unsigned int type; /* GDC type */
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unsigned int refclk; /* disp. reference clock */
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struct mb862xx_gc_mode *gc_mode; /* GDC mode init data */
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int pre_init; /* don't init display if 1 */
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struct i2c_adapter *adap; /* GDC I2C bus adapter */
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int i2c_rs;
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struct mb862xx_l1_cfg l1_cfg;
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int l1_stride;
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u32 pseudo_palette[16];
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};
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extern void mb862xxfb_init_accel(struct fb_info *info, int xres);
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#ifdef CONFIG_FB_MB862XX_I2C
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extern int mb862xx_i2c_init(struct mb862xxfb_par *par);
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extern void mb862xx_i2c_exit(struct mb862xxfb_par *par);
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#else
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static inline int mb862xx_i2c_init(struct mb862xxfb_par *par) { return 0; }
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static inline void mb862xx_i2c_exit(struct mb862xxfb_par *par) { }
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#endif
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#if defined(CONFIG_FB_MB862XX_LIME) && defined(CONFIG_FB_MB862XX_PCI_GDC)
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#error "Select Lime GDC or CoralP/Carmine support, but not both together"
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#endif
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#if defined(CONFIG_FB_MB862XX_LIME)
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#define gdc_read __raw_readl
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#define gdc_write __raw_writel
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#else
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#define gdc_read readl
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#define gdc_write writel
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#endif
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#define inreg(type, off) \
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gdc_read((par->type + (off)))
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#define outreg(type, off, val) \
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gdc_write((val), (par->type + (off)))
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#define pack(a, b) (((a) << 16) | (b))
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#endif /* __KERNEL__ */
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#endif
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