// SPDX-License-Identifier: GPL-2.0+
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/**************************************************************************
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*
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* BRIEF MODULE DESCRIPTION
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* PCI init for Ralink RT2880 solution
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*
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* Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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**************************************************************************
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* May 2007 Bruce Chang
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* Initial Release
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*
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* May 2009 Bruce Chang
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* support RT2880/RT3883 PCIe
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*
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* May 2011 Bruce Chang
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* support RT6855/MT7620 PCIe
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*
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**************************************************************************
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <mt7621.h>
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#include <ralink_regs.h>
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#include "../../pci/pci.h"
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/*
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* These functions and structures provide the BIOS scan and mapping of the PCI
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* devices.
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*/
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#define RALINK_PCIE0_CLK_EN BIT(24)
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#define RALINK_PCIE1_CLK_EN BIT(25)
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#define RALINK_PCIE2_CLK_EN BIT(26)
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#define RALINK_PCI_CONFIG_ADDR 0x20
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#define RALINK_PCI_CONFIG_DATA 0x24
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#define RALINK_PCI_MEMBASE 0x28
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#define RALINK_PCI_IOBASE 0x2C
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#define RALINK_PCIE0_RST BIT(24)
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#define RALINK_PCIE1_RST BIT(25)
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#define RALINK_PCIE2_RST BIT(26)
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#define RALINK_PCI_PCICFG_ADDR 0x0000
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#define RALINK_PCI_PCIMSK_ADDR 0x000C
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#define RT6855_PCIE0_OFFSET 0x2000
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#define RT6855_PCIE1_OFFSET 0x3000
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#define RT6855_PCIE2_OFFSET 0x4000
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#define RALINK_PCI_BAR0SETUP_ADDR 0x0010
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#define RALINK_PCI_IMBASEBAR0_ADDR 0x0018
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#define RALINK_PCI_ID 0x0030
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#define RALINK_PCI_CLASS 0x0034
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#define RALINK_PCI_SUBID 0x0038
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#define RALINK_PCI_STATUS 0x0050
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#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
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#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
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#define RALINK_PCI_MM_MAP_BASE 0x60000000
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#define RALINK_PCI_IO_MAP_BASE 0x1e160000
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#define ASSERT_SYSRST_PCIE(val) \
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do { \
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if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \
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rt_sysc_m32(0, val, RALINK_RSTCTRL); \
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else \
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rt_sysc_m32(val, 0, RALINK_RSTCTRL); \
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} while (0)
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#define DEASSERT_SYSRST_PCIE(val) \
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do { \
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if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \
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rt_sysc_m32(val, 0, RALINK_RSTCTRL); \
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else \
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rt_sysc_m32(0, val, RALINK_RSTCTRL); \
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} while (0)
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#define RALINK_CLKCFG1 0x30
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#define RALINK_RSTCTRL 0x34
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#define RALINK_GPIOMODE 0x60
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#define RALINK_PCIE_CLK_GEN 0x7c
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#define RALINK_PCIE_CLK_GEN1 0x80
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//RALINK_RSTCTRL bit
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#define RALINK_PCIE_RST BIT(23)
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#define RALINK_PCI_RST BIT(24)
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//RALINK_CLKCFG1 bit
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#define RALINK_PCI_CLK_EN BIT(19)
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#define RALINK_PCIE_CLK_EN BIT(21)
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#define MEMORY_BASE 0x0
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static int pcie_link_status = 0;
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/**
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* struct mt7621_pcie_port - PCIe port information
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* @base: IO mapped register base
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* @list: port list
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* @pcie: pointer to PCIe host info
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* @reset: pointer to port reset control
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*/
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struct mt7621_pcie_port {
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void __iomem *base;
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struct list_head list;
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struct mt7621_pcie *pcie;
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struct reset_control *reset;
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};
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/**
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* struct mt7621_pcie - PCIe host information
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* @base: IO Mapped Register Base
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* @io: IO resource
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* @mem: non-prefetchable memory resource
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* @busn: bus range
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* @offset: IO / Memory offset
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* @dev: Pointer to PCIe device
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* @ports: pointer to PCIe port information
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*/
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struct mt7621_pcie {
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void __iomem *base;
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struct device *dev;
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struct resource io;
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struct resource mem;
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struct resource busn;
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struct {
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resource_size_t mem;
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resource_size_t io;
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} offset;
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struct list_head ports;
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};
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static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
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{
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return readl(pcie->base + reg);
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}
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static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
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{
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writel(val, pcie->base + reg);
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}
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static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
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unsigned int func, unsigned int where)
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{
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return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
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(func << 8) | (where & 0xfc) | 0x80000000;
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}
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static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct mt7621_pcie *pcie = bus->sysdata;
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u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where);
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writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
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return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
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}
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struct pci_ops mt7621_pci_ops = {
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.map_bus = mt7621_pcie_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static u32
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read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
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{
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u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
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return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
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}
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static void
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write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
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{
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u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
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pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
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}
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void
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set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
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int start_b, int bits, int val)
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{
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u32 reg = pcie_read(pcie, offset);
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reg &= ~(((1 << bits) - 1) << start_b);
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reg |= val << start_b;
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pcie_write(pcie, reg, offset);
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}
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void
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bypass_pipe_rst(struct mt7621_pcie *pcie)
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{
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/* PCIe Port 0 */
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
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/* PCIe Port 1 */
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
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/* PCIe Port 2 */
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
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}
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void
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set_phy_for_ssc(struct mt7621_pcie *pcie)
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{
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unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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reg = (reg >> 6) & 0x7;
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/* Set PCIe Port0 & Port1 PHY to disable SSC */
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/* Debug Xtal Type */
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
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if (reg <= 5 && reg >= 3) { // 40MHz Xtal
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
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printk("***** Xtal 40MHz *****\n");
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} else { // 25MHz | 20MHz Xtal
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
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if (reg >= 6) {
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printk("***** Xtal 25MHz *****\n");
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
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} else {
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printk("***** Xtal 20MHz *****\n");
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}
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}
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
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if (reg <= 5 && reg >= 3) { // 40MHz Xtal
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
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}
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/* Enable PHY and disable force mode */
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
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/* Set PCIe Port2 PHY to disable SSC */
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/* Debug Xtal Type */
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
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if (reg <= 5 && reg >= 3) { // 40MHz Xtal
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
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} else { // 25MHz | 20MHz Xtal
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
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if (reg >= 6) { // 25MHz Xtal
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
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}
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}
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
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if (reg <= 5 && reg >= 3) { // 40MHz Xtal
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
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}
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/* Enable PHY and disable force mode */
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
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set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
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}
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static void setup_cm_memory_region(struct resource *mem_resource)
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{
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resource_size_t mask;
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if (mips_cps_numiocu(0)) {
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/* FIXME: hardware doesn't accept mask values with 1s after
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* 0s (e.g. 0xffef), so it would be great to warn if that's
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* about to happen */
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mask = ~(mem_resource->end - mem_resource->start);
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write_gcr_reg1_base(mem_resource->start);
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write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
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printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
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(unsigned long long)read_gcr_reg1_base(),
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(unsigned long long)read_gcr_reg1_mask());
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}
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}
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static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct device_node *node = dev->of_node;
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struct of_pci_range_parser parser;
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struct of_pci_range range;
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int err;
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if (of_pci_range_parser_init(&parser, node)) {
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dev_err(dev, "missing \"ranges\" property\n");
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return -EINVAL;
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}
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for_each_of_pci_range(&parser, &range) {
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struct resource *res = NULL;
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switch (range.flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_IO:
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ioremap(range.cpu_addr, range.size);
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res = &pcie->io;
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pcie->offset.io = 0x00000000UL;
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break;
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case IORESOURCE_MEM:
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res = &pcie->mem;
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pcie->offset.mem = 0x00000000UL;
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break;
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}
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if (res != NULL)
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of_pci_range_to_resource(&range, node, res);
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}
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err = of_pci_parse_bus_range(node, &pcie->busn);
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if (err < 0) {
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dev_err(dev, "failed to parse bus ranges property: %d\n", err);
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pcie->busn.name = node->name;
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pcie->busn.start = 0;
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pcie->busn.end = 0xff;
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pcie->busn.flags = IORESOURCE_BUS;
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}
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return 0;
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}
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static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct device_node *node = dev->of_node;
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struct resource regs;
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const char *type;
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int err;
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type = of_get_property(node, "device_type", NULL);
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if (!type || strcmp(type, "pci") != 0) {
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dev_err(dev, "invalid \"device_type\" %s\n", type);
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return -EINVAL;
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}
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err = of_address_to_resource(node, 0, ®s);
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if (err) {
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dev_err(dev, "missing \"reg\" property\n");
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return err;
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}
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pcie->base = devm_ioremap_resource(dev, ®s);
|
if (IS_ERR(pcie->base))
|
return PTR_ERR(pcie->base);
|
|
return 0;
|
}
|
|
static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
|
struct list_head *res)
|
{
|
struct device *dev = pcie->dev;
|
int err;
|
|
pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
|
pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
|
pci_add_resource(res, &pcie->busn);
|
|
err = devm_request_pci_bus_resources(dev, res);
|
if (err < 0)
|
return err;
|
|
return 0;
|
}
|
|
static int mt7621_pcie_register_host(struct pci_host_bridge *host,
|
struct list_head *res)
|
{
|
struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
|
|
list_splice_init(res, &host->windows);
|
host->busnr = pcie->busn.start;
|
host->dev.parent = pcie->dev;
|
host->ops = &mt7621_pci_ops;
|
host->map_irq = of_irq_parse_and_map_pci;
|
host->swizzle_irq = pci_common_swizzle;
|
host->sysdata = pcie;
|
|
return pci_host_probe(host);
|
}
|
|
static int mt7621_pci_probe(struct platform_device *pdev)
|
{
|
struct device *dev = &pdev->dev;
|
struct mt7621_pcie *pcie;
|
struct pci_host_bridge *bridge;
|
int err;
|
u32 val = 0;
|
LIST_HEAD(res);
|
|
if (!dev->of_node)
|
return -ENODEV;
|
|
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
|
if (!bridge)
|
return -ENODEV;
|
|
pcie = pci_host_bridge_priv(bridge);
|
pcie->dev = dev;
|
platform_set_drvdata(pdev, pcie);
|
INIT_LIST_HEAD(&pcie->ports);
|
|
err = mt7621_pcie_parse_dt(pcie);
|
if (err) {
|
dev_err(dev, "Parsing DT failed\n");
|
return err;
|
}
|
|
/* set resources limits */
|
iomem_resource.start = 0;
|
iomem_resource.end = ~0UL; /* no limit */
|
ioport_resource.start = 0;
|
ioport_resource.end = ~0UL; /* no limit */
|
|
val = RALINK_PCIE0_RST;
|
val |= RALINK_PCIE1_RST;
|
val |= RALINK_PCIE2_RST;
|
|
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
|
|
*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
|
*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
|
mdelay(100);
|
*(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
|
mdelay(100);
|
*(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
|
|
mdelay(100);
|
|
val = RALINK_PCIE0_RST;
|
val |= RALINK_PCIE1_RST;
|
val |= RALINK_PCIE2_RST;
|
|
DEASSERT_SYSRST_PCIE(val);
|
|
if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
|
bypass_pipe_rst(pcie);
|
set_phy_for_ssc(pcie);
|
|
val = read_config(pcie, 0, 0x70c);
|
printk("Port 0 N_FTS = %x\n", (unsigned int)val);
|
|
val = read_config(pcie, 1, 0x70c);
|
printk("Port 1 N_FTS = %x\n", (unsigned int)val);
|
|
val = read_config(pcie, 2, 0x70c);
|
printk("Port 2 N_FTS = %x\n", (unsigned int)val);
|
|
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
|
rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
|
|
rt_sysc_m32(0x80000000, 0, RALINK_PCIE_CLK_GEN);
|
rt_sysc_m32(0x7f000000, 0xa << 24, RALINK_PCIE_CLK_GEN1);
|
rt_sysc_m32(0, 0x80000000, RALINK_PCIE_CLK_GEN);
|
|
mdelay(50);
|
rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
|
|
/* Use GPIO control instead of PERST_N */
|
*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
|
mdelay(1000);
|
|
if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
|
printk("PCIE0 no card, disable it(RST&CLK)\n");
|
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
|
rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
|
pcie_link_status &= ~(1<<0);
|
} else {
|
pcie_link_status |= 1<<0;
|
val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
|
val |= (1<<20); // enable pcie1 interrupt
|
pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
|
}
|
|
if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
|
printk("PCIE1 no card, disable it(RST&CLK)\n");
|
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
|
rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
|
pcie_link_status &= ~(1<<1);
|
} else {
|
pcie_link_status |= 1<<1;
|
val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
|
val |= (1<<21); // enable pcie1 interrupt
|
pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
|
}
|
|
if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
|
printk("PCIE2 no card, disable it(RST&CLK)\n");
|
ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
|
rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
|
pcie_link_status &= ~(1<<2);
|
} else {
|
pcie_link_status |= 1<<2;
|
val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
|
val |= (1<<22); // enable pcie2 interrupt
|
pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
|
}
|
|
if (pcie_link_status == 0)
|
return 0;
|
|
/*
|
pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
|
3'b000 x x x
|
3'b001 x x 0
|
3'b010 x 0 x
|
3'b011 x 1 0
|
3'b100 0 x x
|
3'b101 1 x 0
|
3'b110 1 0 x
|
3'b111 2 1 0
|
*/
|
switch (pcie_link_status) {
|
case 2:
|
val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
|
val &= ~0x00ff0000;
|
val |= 0x1 << 16; // port 0
|
val |= 0x0 << 20; // port 1
|
pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
|
break;
|
case 4:
|
val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
|
val &= ~0x0fff0000;
|
val |= 0x1 << 16; //port0
|
val |= 0x2 << 20; //port1
|
val |= 0x0 << 24; //port2
|
pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
|
break;
|
case 5:
|
val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
|
val &= ~0x0fff0000;
|
val |= 0x0 << 16; //port0
|
val |= 0x2 << 20; //port1
|
val |= 0x1 << 24; //port2
|
pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
|
break;
|
case 6:
|
val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
|
val &= ~0x0fff0000;
|
val |= 0x2 << 16; //port0
|
val |= 0x0 << 20; //port1
|
val |= 0x1 << 24; //port2
|
pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
|
break;
|
}
|
|
/*
|
ioport_resource.start = mt7621_res_pci_io1.start;
|
ioport_resource.end = mt7621_res_pci_io1.end;
|
*/
|
|
pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
|
pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
|
|
//PCIe0
|
if ((pcie_link_status & 0x1) != 0) {
|
/* open 7FFF:2G; ENABLE */
|
pcie_write(pcie, 0x7FFF0001,
|
RT6855_PCIE0_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
|
pcie_write(pcie, MEMORY_BASE,
|
RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
|
pcie_write(pcie, 0x06040001,
|
RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS);
|
printk("PCIE0 enabled\n");
|
}
|
|
//PCIe1
|
if ((pcie_link_status & 0x2) != 0) {
|
/* open 7FFF:2G; ENABLE */
|
pcie_write(pcie, 0x7FFF0001,
|
RT6855_PCIE1_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
|
pcie_write(pcie, MEMORY_BASE,
|
RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
|
pcie_write(pcie, 0x06040001,
|
RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS);
|
printk("PCIE1 enabled\n");
|
}
|
|
//PCIe2
|
if ((pcie_link_status & 0x4) != 0) {
|
/* open 7FFF:2G; ENABLE */
|
pcie_write(pcie, 0x7FFF0001,
|
RT6855_PCIE2_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
|
pcie_write(pcie, MEMORY_BASE,
|
RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
|
pcie_write(pcie, 0x06040001,
|
RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS);
|
printk("PCIE2 enabled\n");
|
}
|
|
switch (pcie_link_status) {
|
case 7:
|
val = read_config(pcie, 2, 0x4);
|
write_config(pcie, 2, 0x4, val|0x4);
|
val = read_config(pcie, 2, 0x70c);
|
val &= ~(0xff)<<8;
|
val |= 0x50<<8;
|
write_config(pcie, 2, 0x70c, val);
|
case 3:
|
case 5:
|
case 6:
|
val = read_config(pcie, 1, 0x4);
|
write_config(pcie, 1, 0x4, val|0x4);
|
val = read_config(pcie, 1, 0x70c);
|
val &= ~(0xff)<<8;
|
val |= 0x50<<8;
|
write_config(pcie, 1, 0x70c, val);
|
default:
|
val = read_config(pcie, 0, 0x4);
|
write_config(pcie, 0, 0x4, val|0x4); //bus master enable
|
val = read_config(pcie, 0, 0x70c);
|
val &= ~(0xff)<<8;
|
val |= 0x50<<8;
|
write_config(pcie, 0, 0x70c, val);
|
}
|
|
err = mt7621_pci_parse_request_of_pci_ranges(pcie);
|
if (err) {
|
dev_err(dev, "Error requesting pci resources from ranges");
|
return err;
|
}
|
|
setup_cm_memory_region(&pcie->mem);
|
|
err = mt7621_pcie_request_resources(pcie, &res);
|
if (err) {
|
dev_err(dev, "Error requesting resources\n");
|
return err;
|
}
|
|
err = mt7621_pcie_register_host(bridge, &res);
|
if (err) {
|
dev_err(dev, "Error registering host\n");
|
return err;
|
}
|
|
return 0;
|
}
|
|
static const struct of_device_id mt7621_pci_ids[] = {
|
{ .compatible = "mediatek,mt7621-pci" },
|
{},
|
};
|
MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
|
|
static struct platform_driver mt7621_pci_driver = {
|
.probe = mt7621_pci_probe,
|
.driver = {
|
.name = "mt7621-pci",
|
.of_match_table = of_match_ptr(mt7621_pci_ids),
|
},
|
};
|
|
static int __init mt7621_pci_init(void)
|
{
|
return platform_driver_register(&mt7621_pci_driver);
|
}
|
|
arch_initcall(mt7621_pci_init);
|
