/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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*
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* (C) COPYRIGHT 2018, 2020-2021 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#ifndef _KBASE_HWCNT_GPU_H_
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#define _KBASE_HWCNT_GPU_H_
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#include <linux/types.h>
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struct kbase_device;
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struct kbase_hwcnt_metadata;
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struct kbase_hwcnt_enable_map;
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struct kbase_hwcnt_dump_buffer;
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#define KBASE_HWCNT_V5_BLOCK_TYPE_COUNT 4
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#define KBASE_HWCNT_V5_HEADERS_PER_BLOCK 4
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#define KBASE_HWCNT_V5_DEFAULT_COUNTERS_PER_BLOCK 60
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#define KBASE_HWCNT_V5_DEFAULT_VALUES_PER_BLOCK \
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(KBASE_HWCNT_V5_HEADERS_PER_BLOCK + \
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KBASE_HWCNT_V5_DEFAULT_COUNTERS_PER_BLOCK)
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/** Index of the PRFCNT_EN header into a V5 counter block */
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#define KBASE_HWCNT_V5_PRFCNT_EN_HEADER 2
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/**
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* enum kbase_hwcnt_gpu_group_type - GPU hardware counter group types, used to
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* identify metadata groups.
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* @KBASE_HWCNT_GPU_GROUP_TYPE_V5: GPU V5 group type.
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*/
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enum kbase_hwcnt_gpu_group_type {
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KBASE_HWCNT_GPU_GROUP_TYPE_V5,
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};
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/**
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* enum kbase_hwcnt_gpu_v5_block_type - GPU V5 hardware counter block types,
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* used to identify metadata blocks.
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* @KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_UNDEFINED: Undefined block (e.g. if a
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* counter set that a block
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* doesn't support is used).
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* @KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE: Front End block (Job manager
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* or CSF HW).
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* @KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE2: Secondary Front End block (Job
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* manager or CSF HW).
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* @KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE3: Tertiary Front End block (Job
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* manager or CSF HW).
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* @KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER: Tiler block.
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* @KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC: Shader Core block.
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* @KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC2: Secondary Shader Core block.
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* @KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC3: Tertiary Shader Core block.
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* @KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS: Memsys block.
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* @KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS2: Secondary Memsys block.
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*/
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enum kbase_hwcnt_gpu_v5_block_type {
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KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_UNDEFINED,
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KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE,
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KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE2,
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KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE3,
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KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER,
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KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC,
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KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC2,
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KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC3,
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KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS,
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KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS2,
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};
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/**
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* enum kbase_hwcnt_set - GPU hardware counter sets
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* @KBASE_HWCNT_SET_PRIMARY: The Primary set of counters
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* @KBASE_HWCNT_SET_SECONDARY: The Secondary set of counters
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* @KBASE_HWCNT_SET_TERTIARY: The Tertiary set of counters
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*/
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enum kbase_hwcnt_set {
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KBASE_HWCNT_SET_PRIMARY,
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KBASE_HWCNT_SET_SECONDARY,
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KBASE_HWCNT_SET_TERTIARY,
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};
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/**
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* struct kbase_hwcnt_physical_enable_map - Representation of enable map
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* directly used by GPU.
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* @fe_bm: Front end (JM/CSHW) counters selection bitmask.
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* @shader_bm: Shader counters selection bitmask.
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* @tiler_bm: Tiler counters selection bitmask.
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* @mmu_l2_bm: MMU_L2 counters selection bitmask.
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*/
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struct kbase_hwcnt_physical_enable_map {
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u32 fe_bm;
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u32 shader_bm;
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u32 tiler_bm;
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u32 mmu_l2_bm;
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};
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/*
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* Values for Hardware Counter SET_SELECT value.
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* Directly passed to HW.
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*/
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enum kbase_hwcnt_physical_set {
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KBASE_HWCNT_PHYSICAL_SET_PRIMARY = 0,
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KBASE_HWCNT_PHYSICAL_SET_SECONDARY = 1,
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KBASE_HWCNT_PHYSICAL_SET_TERTIARY = 2,
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};
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/**
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* struct kbase_hwcnt_gpu_info - Information about hwcnt blocks on the GPUs.
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* @l2_count: L2 cache count.
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* @core_mask: Shader core mask. May be sparse.
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* @clk_cnt: Number of clock domains available.
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* @prfcnt_values_per_block: Total entries (header + counters) of performance
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* counter per block.
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*/
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struct kbase_hwcnt_gpu_info {
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size_t l2_count;
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u64 core_mask;
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u8 clk_cnt;
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size_t prfcnt_values_per_block;
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};
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/**
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* struct kbase_hwcnt_curr_config - Current Configuration of HW allocated to the
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* GPU.
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* @num_l2_slices: Current number of L2 slices allocated to the GPU.
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* @shader_present: Current shader present bitmap that is allocated to the GPU.
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*
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* For architectures with the max_config interface available from the Arbiter,
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* the current resources allocated may change during runtime due to a
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* re-partitioning (possible with partition manager). Thus, the HWC needs to be
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* prepared to report any possible set of counters. For this reason the memory
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* layout in the userspace is based on the maximum possible allocation. On the
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* other hand, each partition has just the view of its currently allocated
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* resources. Therefore, it is necessary to correctly map the dumped HWC values
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* from the registers into this maximum memory layout so that it can be exposed
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* to the userspace side correctly.
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*
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* For L2 cache just the number is enough once the allocated ones will be
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* accumulated on the first L2 slots available in the destination buffer.
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*
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* For the correct mapping of the shader cores it is necessary to jump all the
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* L2 cache slots in the destination buffer that are not allocated. But, it is
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* not necessary to add any logic to map the shader cores bitmap into the memory
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* layout because the shader_present allocated will always be a subset of the
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* maximum shader_present. It is possible because:
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* 1 - Partitions are made of slices and they are always ordered from the ones
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* with more shader cores to the ones with less.
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* 2 - The shader cores in a slice are always contiguous.
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* 3 - A partition can only have a contiguous set of slices allocated to it.
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* So, for example, if 4 slices are available in total, 1 with 4 cores, 2 with
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* 3 cores and 1 with 2 cores. The maximum possible shader_present would be:
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* 0x0011|0111|0111|1111 -> note the order and that the shader cores are
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* contiguous in any slice.
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* Supposing that a partition takes the two slices in the middle, the current
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* config shader_present for this partition would be:
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* 0x0111|0111 -> note that this is a subset of the maximum above and the slices
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* are contiguous.
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* Therefore, by directly copying any subset of the maximum possible
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* shader_present the mapping is already achieved.
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*/
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struct kbase_hwcnt_curr_config {
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size_t num_l2_slices;
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u64 shader_present;
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};
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/**
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* kbase_hwcnt_jm_metadata_create() - Create hardware counter metadata for the
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* JM GPUs.
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* @info: Non-NULL pointer to info struct.
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* @counter_set: The performance counter set used.
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* @out_metadata: Non-NULL pointer to where created metadata is stored on
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* success.
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* @out_dump_bytes: Non-NULL pointer to where the size of the GPU counter dump
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* buffer is stored on success.
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*
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* Return: 0 on success, else error code.
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*/
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int kbase_hwcnt_jm_metadata_create(
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const struct kbase_hwcnt_gpu_info *info,
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enum kbase_hwcnt_set counter_set,
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const struct kbase_hwcnt_metadata **out_metadata,
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size_t *out_dump_bytes);
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/**
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* kbase_hwcnt_jm_metadata_destroy() - Destroy JM GPU hardware counter metadata.
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*
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* @metadata: Pointer to metadata to destroy.
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*/
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void kbase_hwcnt_jm_metadata_destroy(
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const struct kbase_hwcnt_metadata *metadata);
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/**
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* kbase_hwcnt_csf_metadata_create() - Create hardware counter metadata for the
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* CSF GPUs.
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* @info: Non-NULL pointer to info struct.
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* @counter_set: The performance counter set used.
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* @out_metadata: Non-NULL pointer to where created metadata is stored on
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* success.
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*
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* Return: 0 on success, else error code.
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*/
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int kbase_hwcnt_csf_metadata_create(
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const struct kbase_hwcnt_gpu_info *info,
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enum kbase_hwcnt_set counter_set,
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const struct kbase_hwcnt_metadata **out_metadata);
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/**
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* kbase_hwcnt_csf_metadata_destroy() - Destroy CSF GPU hardware counter
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* metadata.
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* @metadata: Pointer to metadata to destroy.
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*/
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void kbase_hwcnt_csf_metadata_destroy(
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const struct kbase_hwcnt_metadata *metadata);
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/**
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* kbase_hwcnt_gpu_metadata_create_truncate_64() - Create HWC metadata with HWC
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* block entries truncated
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* to 64.
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*
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* @dst_md: Non-NULL pointer to where created metadata is stored on success.
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* @src_md: Non-NULL pointer to the HWC metadata used as the source to create
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* dst_md.
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*
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* If the total block entries in src_md is 64, metadata dst_md returns NULL
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* since no need to truncate.
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* if the total block entries in src_md is 128, then a new metadata with block
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* entries truncated to 64 will be created for dst_md, which keeps the interface
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* to user clients backward compatible.
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* If the total block entries in src_md is other values, function returns error
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* since it's not supported.
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*
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* Return: 0 on success, else error code.
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*/
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int kbase_hwcnt_gpu_metadata_create_truncate_64(
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const struct kbase_hwcnt_metadata **dst_md,
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const struct kbase_hwcnt_metadata *src_md);
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/**
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* kbase_hwcnt_dump_buffer_copy_strict_narrow() - Copy all enabled values from
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* src to dst.
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*
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* @dst: Non-NULL pointer to dst dump buffer.
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* @src: Non-NULL pointer to src dump buffer.
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* @dst_enable_map: Non-NULL pointer to enable map specifying enabled values.
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*
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* After the operation, all non-enabled values (including padding bytes) will be
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* zero.
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*
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* The dst and src have different metadata, and the dst metadata is narrower
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* than src metadata.
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*/
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void kbase_hwcnt_dump_buffer_copy_strict_narrow(
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struct kbase_hwcnt_dump_buffer *dst,
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const struct kbase_hwcnt_dump_buffer *src,
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const struct kbase_hwcnt_enable_map *dst_enable_map);
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/**
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* kbase_hwcnt_jm_dump_get() - Copy or accumulate enabled counters from the raw
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* dump buffer in src into the dump buffer
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* abstraction in dst.
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* @dst: Non-NULL pointer to dst dump buffer.
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* @src: Non-NULL pointer to src raw dump buffer, of same length
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* as returned in out_dump_bytes parameter of
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* kbase_hwcnt_jm_metadata_create.
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* @dst_enable_map: Non-NULL pointer to enable map specifying enabled values.
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* @pm_core_mask: PM state synchronized shaders core mask with the dump.
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* @curr_config: Current allocated hardware resources to correctly map the
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* src raw dump buffer to the dst dump buffer.
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* @accumulate: True if counters in src should be accumulated into dst,
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* rather than copied.
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*
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* The dst and dst_enable_map MUST have been created from the same metadata as
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* returned from the call to kbase_hwcnt_jm_metadata_create as was used to get
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* the length of src.
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*
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* Return: 0 on success, else error code.
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*/
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int kbase_hwcnt_jm_dump_get(struct kbase_hwcnt_dump_buffer *dst, void *src,
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const struct kbase_hwcnt_enable_map *dst_enable_map,
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const u64 pm_core_mask,
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const struct kbase_hwcnt_curr_config *curr_config,
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bool accumulate);
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/**
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* kbase_hwcnt_csf_dump_get() - Copy or accumulate enabled counters from the raw
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* dump buffer in src into the dump buffer
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* abstraction in dst.
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* @dst: Non-NULL pointer to dst dump buffer.
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* @src: Non-NULL pointer to src raw dump buffer, of same length
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* as returned in out_dump_bytes parameter of
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* kbase_hwcnt_csf_metadata_create.
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* @dst_enable_map: Non-NULL pointer to enable map specifying enabled values.
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* @accumulate: True if counters in src should be accumulated into dst,
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* rather than copied.
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*
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* The dst and dst_enable_map MUST have been created from the same metadata as
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* returned from the call to kbase_hwcnt_csf_metadata_create as was used to get
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* the length of src.
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*
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* Return: 0 on success, else error code.
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*/
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int kbase_hwcnt_csf_dump_get(struct kbase_hwcnt_dump_buffer *dst, void *src,
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const struct kbase_hwcnt_enable_map *dst_enable_map,
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bool accumulate);
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/**
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* kbase_hwcnt_gpu_enable_map_to_physical() - Convert an enable map abstraction
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* into a physical enable map.
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* @dst: Non-NULL pointer to dst physical enable map.
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* @src: Non-NULL pointer to src enable map abstraction.
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*
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* The src must have been created from a metadata returned from a call to
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* kbase_hwcnt_jm_metadata_create or kbase_hwcnt_csf_metadata_create.
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*
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* This is a lossy conversion, as the enable map abstraction has one bit per
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* individual counter block value, but the physical enable map uses 1 bit for
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* every 4 counters, shared over all instances of a block.
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*/
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void kbase_hwcnt_gpu_enable_map_to_physical(
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struct kbase_hwcnt_physical_enable_map *dst,
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const struct kbase_hwcnt_enable_map *src);
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/**
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* kbase_hwcnt_gpu_set_to_physical() - Map counter set selection to physical
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* SET_SELECT value.
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*
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* @dst: Non-NULL pointer to dst physical SET_SELECT value.
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* @src: Non-NULL pointer to src counter set selection.
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*/
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void kbase_hwcnt_gpu_set_to_physical(enum kbase_hwcnt_physical_set *dst,
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enum kbase_hwcnt_set src);
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/**
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* kbase_hwcnt_gpu_enable_map_from_physical() - Convert a physical enable map to
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* an enable map abstraction.
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* @dst: Non-NULL pointer to dst enable map abstraction.
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* @src: Non-NULL pointer to src physical enable map.
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*
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* The dst must have been created from a metadata returned from a call to
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* kbase_hwcnt_jm_metadata_create or kbase_hwcnt_csf_metadata_create.
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*
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* This is a lossy conversion, as the physical enable map can technically
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* support counter blocks with 128 counters each, but no hardware actually uses
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* more than 64, so the enable map abstraction has nowhere to store the enable
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* information for the 64 non-existent counters.
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*/
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void kbase_hwcnt_gpu_enable_map_from_physical(
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struct kbase_hwcnt_enable_map *dst,
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const struct kbase_hwcnt_physical_enable_map *src);
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/**
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* kbase_hwcnt_gpu_patch_dump_headers() - Patch all the performance counter
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* enable headers in a dump buffer to
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* reflect the specified enable map.
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* @buf: Non-NULL pointer to dump buffer to patch.
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* @enable_map: Non-NULL pointer to enable map.
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*
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* The buf and enable_map must have been created from a metadata returned from
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* a call to kbase_hwcnt_jm_metadata_create or kbase_hwcnt_csf_metadata_create.
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*
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* This function should be used before handing off a dump buffer over the
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* kernel-user boundary, to ensure the header is accurate for the enable map
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* used by the user.
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*/
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void kbase_hwcnt_gpu_patch_dump_headers(
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struct kbase_hwcnt_dump_buffer *buf,
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const struct kbase_hwcnt_enable_map *enable_map);
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#endif /* _KBASE_HWCNT_GPU_H_ */
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