// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2018-2021 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include "mali_kbase_hwcnt_backend_jm.h"
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#include "mali_kbase_hwcnt_gpu.h"
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#include "mali_kbase_hwcnt_types.h"
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#include "mali_kbase.h"
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#include "backend/gpu/mali_kbase_pm_ca.h"
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#include "mali_kbase_hwaccess_instr.h"
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#include "mali_kbase_hwaccess_time.h"
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#include "mali_kbase_ccswe.h"
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#include "backend/gpu/mali_kbase_clk_rate_trace_mgr.h"
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#include "backend/gpu/mali_kbase_pm_internal.h"
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/**
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* struct kbase_hwcnt_backend_jm_info - Information used to create an instance
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* of a JM hardware counter backend.
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* @kbdev: KBase device.
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* @counter_set: The performance counter set to use.
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* @metadata: Hardware counter metadata.
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* @dump_bytes: Bytes of GPU memory required to perform a
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* hardware counter dump.
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*/
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struct kbase_hwcnt_backend_jm_info {
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struct kbase_device *kbdev;
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enum kbase_hwcnt_set counter_set;
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const struct kbase_hwcnt_metadata *metadata;
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size_t dump_bytes;
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};
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/**
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* struct kbase_hwcnt_backend_jm - Instance of a JM hardware counter backend.
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* @info: Info used to create the backend.
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* @kctx: KBase context used for GPU memory allocation and
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* counter dumping.
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* @gpu_dump_va: GPU hardware counter dump buffer virtual address.
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* @cpu_dump_va: CPU mapping of gpu_dump_va.
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* @vmap: Dump buffer vmap.
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* @enabled: True if dumping has been enabled, else false.
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* @pm_core_mask: PM state sync-ed shaders core mask for the enabled
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* dumping.
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* @curr_config: Current allocated hardware resources to correctly map the src
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* raw dump buffer to the dst dump buffer.
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* @clk_enable_map: The enable map specifying enabled clock domains.
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* @cycle_count_elapsed:
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* Cycle count elapsed for a given sample period.
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* The top clock cycle, index 0, is read directly from
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* hardware, but the other clock domains need to be
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* calculated with software estimation.
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* @prev_cycle_count: Previous cycle count to calculate the cycle count for
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* sample period.
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* @rate_listener: Clock rate listener callback state.
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* @ccswe_shader_cores: Shader cores cycle count software estimator.
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*/
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struct kbase_hwcnt_backend_jm {
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const struct kbase_hwcnt_backend_jm_info *info;
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struct kbase_context *kctx;
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u64 gpu_dump_va;
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void *cpu_dump_va;
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struct kbase_vmap_struct *vmap;
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bool enabled;
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u64 pm_core_mask;
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struct kbase_hwcnt_curr_config curr_config;
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u64 clk_enable_map;
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u64 cycle_count_elapsed[BASE_MAX_NR_CLOCKS_REGULATORS];
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u64 prev_cycle_count[BASE_MAX_NR_CLOCKS_REGULATORS];
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struct kbase_clk_rate_listener rate_listener;
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struct kbase_ccswe ccswe_shader_cores;
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};
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/**
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* kbasep_hwcnt_backend_jm_gpu_info_init() - Initialise an info structure used
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* to create the hwcnt metadata.
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* @kbdev: Non-NULL pointer to kbase device.
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* @info: Non-NULL pointer to data structure to be filled in.
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*
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* The initialised info struct will only be valid for use while kbdev is valid.
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*/
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static int
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kbasep_hwcnt_backend_jm_gpu_info_init(struct kbase_device *kbdev,
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struct kbase_hwcnt_gpu_info *info)
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{
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size_t clk;
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if (!kbdev || !info)
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return -EINVAL;
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{
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const struct base_gpu_props *props = &kbdev->gpu_props.props;
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const size_t l2_count = props->l2_props.num_l2_slices;
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const size_t core_mask =
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props->coherency_info.group[0].core_mask;
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info->l2_count = l2_count;
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info->core_mask = core_mask;
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info->prfcnt_values_per_block =
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KBASE_HWCNT_V5_DEFAULT_VALUES_PER_BLOCK;
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}
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/* Determine the number of available clock domains. */
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for (clk = 0; clk < BASE_MAX_NR_CLOCKS_REGULATORS; clk++) {
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if (kbdev->pm.clk_rtm.clks[clk] == NULL)
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break;
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}
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info->clk_cnt = clk;
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return 0;
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}
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/**
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* kbasep_hwcnt_backend_jm_on_freq_change() - On freq change callback
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*
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* @rate_listener: Callback state
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* @clk_index: Clock index
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* @clk_rate_hz: Clock frequency(hz)
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*/
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static void kbasep_hwcnt_backend_jm_on_freq_change(
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struct kbase_clk_rate_listener *rate_listener,
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u32 clk_index,
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u32 clk_rate_hz)
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{
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struct kbase_hwcnt_backend_jm *backend_jm = container_of(
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rate_listener, struct kbase_hwcnt_backend_jm, rate_listener);
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u64 timestamp_ns;
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if (clk_index != KBASE_CLOCK_DOMAIN_SHADER_CORES)
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return;
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timestamp_ns = ktime_get_raw_ns();
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kbase_ccswe_freq_change(
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&backend_jm->ccswe_shader_cores, timestamp_ns, clk_rate_hz);
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}
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/**
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* kbasep_hwcnt_backend_jm_cc_enable() - Enable cycle count tracking
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*
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* @backend_jm: Non-NULL pointer to backend.
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* @enable_map: Non-NULL pointer to enable map specifying enabled counters.
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* @timestamp_ns: Timestamp(ns) when HWCNT were enabled.
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*/
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static void kbasep_hwcnt_backend_jm_cc_enable(
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struct kbase_hwcnt_backend_jm *backend_jm,
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const struct kbase_hwcnt_enable_map *enable_map,
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u64 timestamp_ns)
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{
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struct kbase_device *kbdev = backend_jm->kctx->kbdev;
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u64 clk_enable_map = enable_map->clk_enable_map;
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u64 cycle_count;
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if (kbase_hwcnt_clk_enable_map_enabled(
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clk_enable_map, KBASE_CLOCK_DOMAIN_TOP)) {
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/* turn on the cycle counter */
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kbase_pm_request_gpu_cycle_counter_l2_is_on(kbdev);
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/* Read cycle count for top clock domain. */
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kbase_backend_get_gpu_time_norequest(
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kbdev, &cycle_count, NULL, NULL);
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backend_jm->prev_cycle_count[KBASE_CLOCK_DOMAIN_TOP] =
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cycle_count;
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}
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if (kbase_hwcnt_clk_enable_map_enabled(
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clk_enable_map, KBASE_CLOCK_DOMAIN_SHADER_CORES)) {
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/* software estimation for non-top clock domains */
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struct kbase_clk_rate_trace_manager *rtm = &kbdev->pm.clk_rtm;
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const struct kbase_clk_data *clk_data =
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rtm->clks[KBASE_CLOCK_DOMAIN_SHADER_CORES];
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u32 cur_freq;
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unsigned long flags;
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spin_lock_irqsave(&rtm->lock, flags);
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cur_freq = (u32) clk_data->clock_val;
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kbase_ccswe_reset(&backend_jm->ccswe_shader_cores);
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kbase_ccswe_freq_change(
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&backend_jm->ccswe_shader_cores,
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timestamp_ns,
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cur_freq);
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kbase_clk_rate_trace_manager_subscribe_no_lock(
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rtm, &backend_jm->rate_listener);
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spin_unlock_irqrestore(&rtm->lock, flags);
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/* ccswe was reset. The estimated cycle is zero. */
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backend_jm->prev_cycle_count[
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KBASE_CLOCK_DOMAIN_SHADER_CORES] = 0;
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}
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/* Keep clk_enable_map for dump_request. */
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backend_jm->clk_enable_map = clk_enable_map;
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}
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/**
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* kbasep_hwcnt_backend_jm_cc_disable() - Disable cycle count tracking
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*
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* @backend_jm: Non-NULL pointer to backend.
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*/
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static void kbasep_hwcnt_backend_jm_cc_disable(
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struct kbase_hwcnt_backend_jm *backend_jm)
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{
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struct kbase_device *kbdev = backend_jm->kctx->kbdev;
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struct kbase_clk_rate_trace_manager *rtm = &kbdev->pm.clk_rtm;
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u64 clk_enable_map = backend_jm->clk_enable_map;
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if (kbase_hwcnt_clk_enable_map_enabled(
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clk_enable_map, KBASE_CLOCK_DOMAIN_TOP)) {
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/* turn off the cycle counter */
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kbase_pm_release_gpu_cycle_counter(kbdev);
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}
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if (kbase_hwcnt_clk_enable_map_enabled(
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clk_enable_map, KBASE_CLOCK_DOMAIN_SHADER_CORES)) {
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kbase_clk_rate_trace_manager_unsubscribe(
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rtm, &backend_jm->rate_listener);
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}
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}
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/**
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* kbasep_hwcnt_gpu_update_curr_config() - Update the destination buffer with
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* current config information.
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* @kbdev: Non-NULL pointer to kbase device.
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* @curr_config: Non-NULL pointer to return the current configuration of
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* hardware allocated to the GPU.
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*
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* The current configuration information is used for architectures where the
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* max_config interface is available from the Arbiter. In this case the current
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* allocated hardware is not always the same, so the current config information
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* is used to correctly map the current allocated resources to the memory layout
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* that is copied to the user space.
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*
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* Return: 0 on success, else error code.
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*/
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static int kbasep_hwcnt_gpu_update_curr_config(
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struct kbase_device *kbdev,
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struct kbase_hwcnt_curr_config *curr_config)
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{
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if (WARN_ON(!kbdev) || WARN_ON(!curr_config))
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return -EINVAL;
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lockdep_assert_held(&kbdev->hwaccess_lock);
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curr_config->num_l2_slices =
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kbdev->gpu_props.curr_config.l2_slices;
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curr_config->shader_present =
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kbdev->gpu_props.curr_config.shader_present;
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return 0;
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}
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/* JM backend implementation of kbase_hwcnt_backend_timestamp_ns_fn */
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static u64 kbasep_hwcnt_backend_jm_timestamp_ns(
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struct kbase_hwcnt_backend *backend)
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{
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(void)backend;
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return ktime_get_raw_ns();
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}
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/* JM backend implementation of kbase_hwcnt_backend_dump_enable_nolock_fn */
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static int kbasep_hwcnt_backend_jm_dump_enable_nolock(
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struct kbase_hwcnt_backend *backend,
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const struct kbase_hwcnt_enable_map *enable_map)
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{
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int errcode;
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struct kbase_hwcnt_backend_jm *backend_jm =
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(struct kbase_hwcnt_backend_jm *)backend;
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struct kbase_context *kctx;
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struct kbase_device *kbdev;
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struct kbase_hwcnt_physical_enable_map phys_enable_map;
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enum kbase_hwcnt_physical_set phys_counter_set;
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struct kbase_instr_hwcnt_enable enable;
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u64 timestamp_ns;
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if (!backend_jm || !enable_map || backend_jm->enabled ||
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(enable_map->metadata != backend_jm->info->metadata))
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return -EINVAL;
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kctx = backend_jm->kctx;
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kbdev = backend_jm->kctx->kbdev;
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lockdep_assert_held(&kbdev->hwaccess_lock);
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kbase_hwcnt_gpu_enable_map_to_physical(&phys_enable_map, enable_map);
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kbase_hwcnt_gpu_set_to_physical(&phys_counter_set,
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backend_jm->info->counter_set);
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enable.fe_bm = phys_enable_map.fe_bm;
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enable.shader_bm = phys_enable_map.shader_bm;
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enable.tiler_bm = phys_enable_map.tiler_bm;
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enable.mmu_l2_bm = phys_enable_map.mmu_l2_bm;
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enable.counter_set = phys_counter_set;
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enable.dump_buffer = backend_jm->gpu_dump_va;
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enable.dump_buffer_bytes = backend_jm->info->dump_bytes;
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timestamp_ns = kbasep_hwcnt_backend_jm_timestamp_ns(backend);
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/* Update the current configuration information. */
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errcode = kbasep_hwcnt_gpu_update_curr_config(kbdev,
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&backend_jm->curr_config);
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if (errcode)
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goto error;
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errcode = kbase_instr_hwcnt_enable_internal(kbdev, kctx, &enable);
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if (errcode)
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goto error;
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backend_jm->pm_core_mask = kbase_pm_ca_get_instr_core_mask(kbdev);
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backend_jm->enabled = true;
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kbasep_hwcnt_backend_jm_cc_enable(backend_jm, enable_map, timestamp_ns);
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return 0;
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error:
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return errcode;
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}
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/* JM backend implementation of kbase_hwcnt_backend_dump_enable_fn */
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static int kbasep_hwcnt_backend_jm_dump_enable(
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struct kbase_hwcnt_backend *backend,
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const struct kbase_hwcnt_enable_map *enable_map)
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{
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unsigned long flags;
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int errcode;
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struct kbase_hwcnt_backend_jm *backend_jm =
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(struct kbase_hwcnt_backend_jm *)backend;
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struct kbase_device *kbdev;
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if (!backend_jm)
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return -EINVAL;
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kbdev = backend_jm->kctx->kbdev;
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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errcode = kbasep_hwcnt_backend_jm_dump_enable_nolock(
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backend, enable_map);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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return errcode;
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}
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/* JM backend implementation of kbase_hwcnt_backend_dump_disable_fn */
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static void kbasep_hwcnt_backend_jm_dump_disable(
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struct kbase_hwcnt_backend *backend)
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{
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int errcode;
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struct kbase_hwcnt_backend_jm *backend_jm =
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(struct kbase_hwcnt_backend_jm *)backend;
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if (WARN_ON(!backend_jm) || !backend_jm->enabled)
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return;
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kbasep_hwcnt_backend_jm_cc_disable(backend_jm);
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errcode = kbase_instr_hwcnt_disable_internal(backend_jm->kctx);
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WARN_ON(errcode);
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backend_jm->enabled = false;
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}
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/* JM backend implementation of kbase_hwcnt_backend_dump_clear_fn */
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static int kbasep_hwcnt_backend_jm_dump_clear(
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struct kbase_hwcnt_backend *backend)
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{
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struct kbase_hwcnt_backend_jm *backend_jm =
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(struct kbase_hwcnt_backend_jm *)backend;
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if (!backend_jm || !backend_jm->enabled)
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return -EINVAL;
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return kbase_instr_hwcnt_clear(backend_jm->kctx);
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}
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/* JM backend implementation of kbase_hwcnt_backend_dump_request_fn */
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static int kbasep_hwcnt_backend_jm_dump_request(
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struct kbase_hwcnt_backend *backend,
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u64 *dump_time_ns)
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{
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struct kbase_hwcnt_backend_jm *backend_jm =
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(struct kbase_hwcnt_backend_jm *)backend;
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struct kbase_device *kbdev;
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const struct kbase_hwcnt_metadata *metadata;
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u64 current_cycle_count;
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size_t clk;
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int ret;
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if (!backend_jm || !backend_jm->enabled || !dump_time_ns)
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return -EINVAL;
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kbdev = backend_jm->kctx->kbdev;
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metadata = backend_jm->info->metadata;
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/* Disable pre-emption, to make the timestamp as accurate as possible */
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preempt_disable();
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{
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*dump_time_ns = kbasep_hwcnt_backend_jm_timestamp_ns(backend);
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ret = kbase_instr_hwcnt_request_dump(backend_jm->kctx);
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kbase_hwcnt_metadata_for_each_clock(metadata, clk) {
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if (!kbase_hwcnt_clk_enable_map_enabled(
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backend_jm->clk_enable_map, clk))
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continue;
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if (clk == KBASE_CLOCK_DOMAIN_TOP) {
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/* Read cycle count for top clock domain. */
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kbase_backend_get_gpu_time_norequest(
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kbdev, ¤t_cycle_count,
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NULL, NULL);
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} else {
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/*
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* Estimate cycle count for non-top clock
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* domain.
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*/
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current_cycle_count = kbase_ccswe_cycle_at(
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&backend_jm->ccswe_shader_cores,
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*dump_time_ns);
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}
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backend_jm->cycle_count_elapsed[clk] =
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current_cycle_count -
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backend_jm->prev_cycle_count[clk];
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/*
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* Keep the current cycle count for later calculation.
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*/
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backend_jm->prev_cycle_count[clk] = current_cycle_count;
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}
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}
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preempt_enable();
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return ret;
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}
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/* JM backend implementation of kbase_hwcnt_backend_dump_wait_fn */
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static int kbasep_hwcnt_backend_jm_dump_wait(
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struct kbase_hwcnt_backend *backend)
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{
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struct kbase_hwcnt_backend_jm *backend_jm =
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(struct kbase_hwcnt_backend_jm *)backend;
|
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if (!backend_jm || !backend_jm->enabled)
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return -EINVAL;
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return kbase_instr_hwcnt_wait_for_dump(backend_jm->kctx);
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}
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/* JM backend implementation of kbase_hwcnt_backend_dump_get_fn */
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static int kbasep_hwcnt_backend_jm_dump_get(
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struct kbase_hwcnt_backend *backend,
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struct kbase_hwcnt_dump_buffer *dst,
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const struct kbase_hwcnt_enable_map *dst_enable_map,
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bool accumulate)
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{
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struct kbase_hwcnt_backend_jm *backend_jm =
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(struct kbase_hwcnt_backend_jm *)backend;
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size_t clk;
|
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if (!backend_jm || !dst || !dst_enable_map ||
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(backend_jm->info->metadata != dst->metadata) ||
|
(dst_enable_map->metadata != dst->metadata))
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return -EINVAL;
|
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/* Invalidate the kernel buffer before reading from it. */
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kbase_sync_mem_regions(
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backend_jm->kctx, backend_jm->vmap, KBASE_SYNC_TO_CPU);
|
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kbase_hwcnt_metadata_for_each_clock(dst_enable_map->metadata, clk) {
|
if (!kbase_hwcnt_clk_enable_map_enabled(
|
dst_enable_map->clk_enable_map, clk))
|
continue;
|
|
/* Extract elapsed cycle count for each clock domain. */
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dst->clk_cnt_buf[clk] = backend_jm->cycle_count_elapsed[clk];
|
}
|
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return kbase_hwcnt_jm_dump_get(dst, backend_jm->cpu_dump_va,
|
dst_enable_map, backend_jm->pm_core_mask,
|
&backend_jm->curr_config, accumulate);
|
}
|
|
/**
|
* kbasep_hwcnt_backend_jm_dump_alloc() - Allocate a GPU dump buffer.
|
* @info: Non-NULL pointer to JM backend info.
|
* @kctx: Non-NULL pointer to kbase context.
|
* @gpu_dump_va: Non-NULL pointer to where GPU dump buffer virtual address
|
* is stored on success.
|
*
|
* Return: 0 on success, else error code.
|
*/
|
static int kbasep_hwcnt_backend_jm_dump_alloc(
|
const struct kbase_hwcnt_backend_jm_info *info,
|
struct kbase_context *kctx,
|
u64 *gpu_dump_va)
|
{
|
struct kbase_va_region *reg;
|
u64 flags;
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u64 nr_pages;
|
|
WARN_ON(!info);
|
WARN_ON(!kctx);
|
WARN_ON(!gpu_dump_va);
|
|
flags = BASE_MEM_PROT_CPU_RD |
|
BASE_MEM_PROT_GPU_WR |
|
BASEP_MEM_PERMANENT_KERNEL_MAPPING |
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BASE_MEM_CACHED_CPU |
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BASE_MEM_UNCACHED_GPU;
|
|
nr_pages = PFN_UP(info->dump_bytes);
|
|
reg = kbase_mem_alloc(kctx, nr_pages, nr_pages, 0, &flags, gpu_dump_va);
|
|
if (!reg)
|
return -ENOMEM;
|
|
return 0;
|
}
|
|
/**
|
* kbasep_hwcnt_backend_jm_dump_free() - Free an allocated GPU dump buffer.
|
* @kctx: Non-NULL pointer to kbase context.
|
* @gpu_dump_va: GPU dump buffer virtual address.
|
*/
|
static void kbasep_hwcnt_backend_jm_dump_free(
|
struct kbase_context *kctx,
|
u64 gpu_dump_va)
|
{
|
WARN_ON(!kctx);
|
if (gpu_dump_va)
|
kbase_mem_free(kctx, gpu_dump_va);
|
}
|
|
/**
|
* kbasep_hwcnt_backend_jm_destroy() - Destroy a JM backend.
|
* @backend: Pointer to JM backend to destroy.
|
*
|
* Can be safely called on a backend in any state of partial construction.
|
*/
|
static void kbasep_hwcnt_backend_jm_destroy(
|
struct kbase_hwcnt_backend_jm *backend)
|
{
|
if (!backend)
|
return;
|
|
if (backend->kctx) {
|
struct kbase_context *kctx = backend->kctx;
|
struct kbase_device *kbdev = kctx->kbdev;
|
|
if (backend->cpu_dump_va)
|
kbase_phy_alloc_mapping_put(kctx, backend->vmap);
|
|
if (backend->gpu_dump_va)
|
kbasep_hwcnt_backend_jm_dump_free(
|
kctx, backend->gpu_dump_va);
|
|
kbasep_js_release_privileged_ctx(kbdev, kctx);
|
kbase_destroy_context(kctx);
|
}
|
|
kfree(backend);
|
}
|
|
/**
|
* kbasep_hwcnt_backend_jm_create() - Create a JM backend.
|
* @info: Non-NULL pointer to backend info.
|
* @out_backend: Non-NULL pointer to where backend is stored on success.
|
*
|
* Return: 0 on success, else error code.
|
*/
|
static int kbasep_hwcnt_backend_jm_create(
|
const struct kbase_hwcnt_backend_jm_info *info,
|
struct kbase_hwcnt_backend_jm **out_backend)
|
{
|
int errcode;
|
struct kbase_device *kbdev;
|
struct kbase_hwcnt_backend_jm *backend = NULL;
|
|
WARN_ON(!info);
|
WARN_ON(!out_backend);
|
|
kbdev = info->kbdev;
|
|
backend = kzalloc(sizeof(*backend), GFP_KERNEL);
|
if (!backend)
|
goto alloc_error;
|
|
backend->info = info;
|
|
backend->kctx = kbase_create_context(kbdev, true,
|
BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED, 0, NULL);
|
if (!backend->kctx)
|
goto alloc_error;
|
|
kbasep_js_schedule_privileged_ctx(kbdev, backend->kctx);
|
|
errcode = kbasep_hwcnt_backend_jm_dump_alloc(
|
info, backend->kctx, &backend->gpu_dump_va);
|
if (errcode)
|
goto error;
|
|
backend->cpu_dump_va = kbase_phy_alloc_mapping_get(backend->kctx,
|
backend->gpu_dump_va, &backend->vmap);
|
if (!backend->cpu_dump_va)
|
goto alloc_error;
|
|
kbase_ccswe_init(&backend->ccswe_shader_cores);
|
backend->rate_listener.notify = kbasep_hwcnt_backend_jm_on_freq_change;
|
|
|
*out_backend = backend;
|
return 0;
|
|
alloc_error:
|
errcode = -ENOMEM;
|
error:
|
kbasep_hwcnt_backend_jm_destroy(backend);
|
return errcode;
|
}
|
|
/* JM backend implementation of kbase_hwcnt_backend_metadata_fn */
|
static const struct kbase_hwcnt_metadata *
|
kbasep_hwcnt_backend_jm_metadata(const struct kbase_hwcnt_backend_info *info)
|
{
|
if (!info)
|
return NULL;
|
|
return ((const struct kbase_hwcnt_backend_jm_info *)info)->metadata;
|
}
|
|
/* JM backend implementation of kbase_hwcnt_backend_init_fn */
|
static int kbasep_hwcnt_backend_jm_init(
|
const struct kbase_hwcnt_backend_info *info,
|
struct kbase_hwcnt_backend **out_backend)
|
{
|
int errcode;
|
struct kbase_hwcnt_backend_jm *backend = NULL;
|
|
if (!info || !out_backend)
|
return -EINVAL;
|
|
errcode = kbasep_hwcnt_backend_jm_create(
|
(const struct kbase_hwcnt_backend_jm_info *) info, &backend);
|
if (errcode)
|
return errcode;
|
|
*out_backend = (struct kbase_hwcnt_backend *)backend;
|
|
return 0;
|
}
|
|
/* JM backend implementation of kbase_hwcnt_backend_term_fn */
|
static void kbasep_hwcnt_backend_jm_term(struct kbase_hwcnt_backend *backend)
|
{
|
if (!backend)
|
return;
|
|
kbasep_hwcnt_backend_jm_dump_disable(backend);
|
kbasep_hwcnt_backend_jm_destroy(
|
(struct kbase_hwcnt_backend_jm *)backend);
|
}
|
|
/**
|
* kbasep_hwcnt_backend_jm_info_destroy() - Destroy a JM backend info.
|
* @info: Pointer to info to destroy.
|
*
|
* Can be safely called on a backend info in any state of partial construction.
|
*/
|
static void kbasep_hwcnt_backend_jm_info_destroy(
|
const struct kbase_hwcnt_backend_jm_info *info)
|
{
|
if (!info)
|
return;
|
|
kbase_hwcnt_jm_metadata_destroy(info->metadata);
|
kfree(info);
|
}
|
|
/**
|
* kbasep_hwcnt_backend_jm_info_create() - Create a JM backend info.
|
* @kbdev: Non_NULL pointer to kbase device.
|
* @out_info: Non-NULL pointer to where info is stored on success.
|
*
|
* Return 0 on success, else error code.
|
*/
|
static int kbasep_hwcnt_backend_jm_info_create(
|
struct kbase_device *kbdev,
|
const struct kbase_hwcnt_backend_jm_info **out_info)
|
{
|
int errcode = -ENOMEM;
|
struct kbase_hwcnt_gpu_info hwcnt_gpu_info;
|
struct kbase_hwcnt_backend_jm_info *info = NULL;
|
|
WARN_ON(!kbdev);
|
WARN_ON(!out_info);
|
|
errcode = kbasep_hwcnt_backend_jm_gpu_info_init(kbdev, &hwcnt_gpu_info);
|
if (errcode)
|
return errcode;
|
|
info = kzalloc(sizeof(*info), GFP_KERNEL);
|
if (!info)
|
goto error;
|
|
info->kbdev = kbdev;
|
|
#ifdef CONFIG_MALI_BIFROST_PRFCNT_SET_SECONDARY
|
info->counter_set = KBASE_HWCNT_SET_SECONDARY;
|
#elif defined(CONFIG_MALI_PRFCNT_SET_TERTIARY)
|
info->counter_set = KBASE_HWCNT_SET_TERTIARY;
|
#else
|
/* Default to primary */
|
info->counter_set = KBASE_HWCNT_SET_PRIMARY;
|
#endif
|
|
errcode = kbase_hwcnt_jm_metadata_create(&hwcnt_gpu_info,
|
info->counter_set,
|
&info->metadata,
|
&info->dump_bytes);
|
if (errcode)
|
goto error;
|
|
*out_info = info;
|
|
return 0;
|
error:
|
kbasep_hwcnt_backend_jm_info_destroy(info);
|
return errcode;
|
}
|
|
int kbase_hwcnt_backend_jm_create(
|
struct kbase_device *kbdev,
|
struct kbase_hwcnt_backend_interface *iface)
|
{
|
int errcode;
|
const struct kbase_hwcnt_backend_jm_info *info = NULL;
|
|
if (!kbdev || !iface)
|
return -EINVAL;
|
|
errcode = kbasep_hwcnt_backend_jm_info_create(kbdev, &info);
|
|
if (errcode)
|
return errcode;
|
|
iface->info = (struct kbase_hwcnt_backend_info *)info;
|
iface->metadata = kbasep_hwcnt_backend_jm_metadata;
|
iface->init = kbasep_hwcnt_backend_jm_init;
|
iface->term = kbasep_hwcnt_backend_jm_term;
|
iface->timestamp_ns = kbasep_hwcnt_backend_jm_timestamp_ns;
|
iface->dump_enable = kbasep_hwcnt_backend_jm_dump_enable;
|
iface->dump_enable_nolock = kbasep_hwcnt_backend_jm_dump_enable_nolock;
|
iface->dump_disable = kbasep_hwcnt_backend_jm_dump_disable;
|
iface->dump_clear = kbasep_hwcnt_backend_jm_dump_clear;
|
iface->dump_request = kbasep_hwcnt_backend_jm_dump_request;
|
iface->dump_wait = kbasep_hwcnt_backend_jm_dump_wait;
|
iface->dump_get = kbasep_hwcnt_backend_jm_dump_get;
|
|
return 0;
|
}
|
|
void kbase_hwcnt_backend_jm_destroy(
|
struct kbase_hwcnt_backend_interface *iface)
|
{
|
if (!iface)
|
return;
|
|
kbasep_hwcnt_backend_jm_info_destroy(
|
(const struct kbase_hwcnt_backend_jm_info *)iface->info);
|
memset(iface, 0, sizeof(*iface));
|
}
|
