// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2014-2016, 2018-2021 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include <mali_kbase.h>
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#include <gpu/mali_kbase_gpu_fault.h>
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#include <backend/gpu/mali_kbase_instr_internal.h>
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#include <backend/gpu/mali_kbase_pm_internal.h>
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#include <device/mali_kbase_device.h>
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#include <mali_kbase_reset_gpu.h>
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#include <mmu/mali_kbase_mmu.h>
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#if !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI)
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void kbase_reg_write(struct kbase_device *kbdev, u32 offset, u32 value)
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{
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KBASE_DEBUG_ASSERT(kbdev->pm.backend.gpu_powered);
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KBASE_DEBUG_ASSERT(kbdev->dev != NULL);
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writel(value, kbdev->reg + offset);
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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if (unlikely(kbdev->io_history.enabled))
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kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
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value, 1);
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#endif /* CONFIG_DEBUG_FS */
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dev_dbg(kbdev->dev, "w: reg %08x val %08x", offset, value);
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}
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KBASE_EXPORT_TEST_API(kbase_reg_write);
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u32 kbase_reg_read(struct kbase_device *kbdev, u32 offset)
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{
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u32 val;
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KBASE_DEBUG_ASSERT(kbdev->pm.backend.gpu_powered);
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KBASE_DEBUG_ASSERT(kbdev->dev != NULL);
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val = readl(kbdev->reg + offset);
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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if (unlikely(kbdev->io_history.enabled))
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kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
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val, 0);
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#endif /* CONFIG_DEBUG_FS */
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dev_dbg(kbdev->dev, "r: reg %08x val %08x", offset, val);
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return val;
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}
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KBASE_EXPORT_TEST_API(kbase_reg_read);
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bool kbase_is_gpu_removed(struct kbase_device *kbdev)
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{
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u32 val;
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val = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID));
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return val == 0;
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}
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#endif /* !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI) */
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void kbase_gpu_start_cache_clean_nolock(struct kbase_device *kbdev)
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{
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u32 irq_mask;
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lockdep_assert_held(&kbdev->hwaccess_lock);
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if (kbdev->cache_clean_in_progress) {
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/* If this is called while another clean is in progress, we
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* can't rely on the current one to flush any new changes in
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* the cache. Instead, trigger another cache clean immediately
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* after this one finishes.
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*/
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kbdev->cache_clean_queued = true;
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return;
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}
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/* Enable interrupt */
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irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK));
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kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK),
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irq_mask | CLEAN_CACHES_COMPLETED);
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KBASE_KTRACE_ADD(kbdev, CORE_GPU_CLEAN_INV_CACHES, NULL, 0);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND),
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GPU_COMMAND_CLEAN_INV_CACHES);
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kbdev->cache_clean_in_progress = true;
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}
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void kbase_gpu_start_cache_clean(struct kbase_device *kbdev)
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{
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unsigned long flags;
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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kbase_gpu_start_cache_clean_nolock(kbdev);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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}
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void kbase_gpu_cache_clean_wait_complete(struct kbase_device *kbdev)
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{
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lockdep_assert_held(&kbdev->hwaccess_lock);
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kbdev->cache_clean_queued = false;
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kbdev->cache_clean_in_progress = false;
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wake_up(&kbdev->cache_clean_wait);
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}
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void kbase_clean_caches_done(struct kbase_device *kbdev)
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{
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u32 irq_mask;
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unsigned long flags;
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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if (kbdev->cache_clean_queued) {
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kbdev->cache_clean_queued = false;
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KBASE_KTRACE_ADD(kbdev, CORE_GPU_CLEAN_INV_CACHES, NULL, 0);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND),
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GPU_COMMAND_CLEAN_INV_CACHES);
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} else {
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/* Disable interrupt */
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irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK));
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kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK),
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irq_mask & ~CLEAN_CACHES_COMPLETED);
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kbase_gpu_cache_clean_wait_complete(kbdev);
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}
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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}
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static inline bool get_cache_clean_flag(struct kbase_device *kbdev)
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{
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bool cache_clean_in_progress;
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unsigned long flags;
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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cache_clean_in_progress = kbdev->cache_clean_in_progress;
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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return cache_clean_in_progress;
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}
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void kbase_gpu_wait_cache_clean(struct kbase_device *kbdev)
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{
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while (get_cache_clean_flag(kbdev)) {
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wait_event_interruptible(kbdev->cache_clean_wait,
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!kbdev->cache_clean_in_progress);
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}
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}
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int kbase_gpu_wait_cache_clean_timeout(struct kbase_device *kbdev,
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unsigned int wait_timeout_ms)
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{
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long remaining = msecs_to_jiffies(wait_timeout_ms);
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while (remaining && get_cache_clean_flag(kbdev)) {
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remaining = wait_event_timeout(kbdev->cache_clean_wait,
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!kbdev->cache_clean_in_progress,
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remaining);
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}
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return (remaining ? 0 : -ETIMEDOUT);
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}
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