ROCKCHIP MIPI DPHY WITH INNO IP BLOCK
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Required properties:
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- compatible : must be one of:
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"rockchip,rk1808-mipi-dphy";
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"rockchip,rv1126-mipi-dphy";
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- reg : the address offset of register for mipi-dphy configuration.
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- #phy-cells : must be 0. See ./phy-bindings.txt for details.
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- clocks and clock-names:
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- the "pclk" clock is required by the phy module, used to register
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configuration
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- the "ref" clock is used to get the rate of the reference clock
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provided to the PHY module
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- clock-output-names: from common clock binding.
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See ../clocks/clock-bindings.txt for details.
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- #clock-cells : from common clock binding; shall be set to 0.
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- resets : phandle to the reset of MIPI DSI PHY APB clock.
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- reset-names : should be "apb".
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Example:
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mipi_dphy: mipi-dphy@ff370000 {
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compatible = "rockchip,rk1808-mipi-dphy";
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reg = <0x0 0xff370000 0x0 0x500>;
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clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
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clock-names = "ref", "pclk";
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clock-output-names = "mipi_dphy_pll";
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#clock-cells = <0>;
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resets = <&cru SRST_MIPIDSIPHY_P>;
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reset-names = "apb";
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#phy-cells = <0>;
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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