Rockchip IOMMU
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==============
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A Rockchip DRM iommu translates io virtual addresses to physical addresses for
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its master device. Each slave device is bound to a single master device, and
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shares its clocks, power domain and irq.
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Required properties:
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- compatible : Should be "rockchip,iommu"
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- reg : Address space for the configuration registers
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- interrupts : Interrupt specifier for the IOMMU instance
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- interrupt-names : Interrupt name for the IOMMU instance
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- #iommu-cells : Should be <0>. This indicates the iommu is a
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"single-master" device, and needs no additional information
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to associate with its master device. See:
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Documentation/devicetree/bindings/iommu/iommu.txt
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- clocks : A list of clocks required for the IOMMU to be accessible by
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the host CPU.
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- clock-names : Should contain the following:
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"iface" - Main peripheral bus clock (PCLK/HCL) (required)
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"aclk" - AXI bus clock (required)
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Optional properties:
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- rockchip,disable-mmu-reset : Don't use the mmu reset operation.
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Some mmu instances may produce unexpected results
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when the reset operation is used.
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- rk_iommu,disable_reset_quirk : Same with above, for compatible with previous code
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- rockchip,skip-mmu-read : Some iommu instances are not able to be read, skip
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reading operation to make iommu work as normal
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Example:
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vopl_mmu: iommu@ff940300 {
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compatible = "rockchip,iommu";
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reg = <0xff940300 0x100>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vopl_mmu";
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clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
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clock-names = "aclk", "iface";
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#iommu-cells = <0>;
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};
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