From b92c22b144d063c4436a6693045ceb57d344c495 Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <claziss@synopsys.com>
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Date: Wed, 11 Nov 2020 12:31:10 +0200
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Subject: [PATCH] arc: Refurbish adc/sbc patterns
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The adc/sbc patterns were unecessary spliting, remove that and
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associated functions.
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gcc/ChangeLog:
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2020-10-11 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc-protos.h (arc_scheduling_not_expected): Remove
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it.
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(arc_sets_cc_p): Likewise.
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(arc_need_delay): Likewise.
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* config/arc/arc.c (arc_sets_cc_p): Likewise.
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(arc_need_delay): Likewise.
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(arc_scheduling_not_expected): Likewise.
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* config/arc/arc.md: Convert adc/sbc patterns to simple
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instruction definitions.
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Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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Downloaded from upstream commit
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https://github.com/foss-for-synopsys-dwc-arc-processors/gcc/commit/b92c22b144d063c4436a6693045ceb57d344c495
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Signed-off-by: Bernd Kuhls <bernd.kuhls@t-online.de>
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---
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gcc/config/arc/arc-protos.h | 3 --
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gcc/config/arc/arc.c | 53 ---------------------
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gcc/config/arc/arc.md | 95 +++++++++++--------------------------
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3 files changed, 29 insertions(+), 122 deletions(-)
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diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
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index c72d78e3b9e..de4cf47c818 100644
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--- a/gcc/config/arc/arc-protos.h
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+++ b/gcc/config/arc/arc-protos.h
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@@ -90,10 +90,7 @@ extern void split_subsi (rtx *);
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extern void arc_split_move (rtx *);
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extern const char *arc_short_long (rtx_insn *insn, const char *, const char *);
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extern rtx arc_regno_use_in (unsigned int, rtx);
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-extern bool arc_scheduling_not_expected (void);
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-extern bool arc_sets_cc_p (rtx_insn *insn);
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extern int arc_label_align (rtx_insn *label);
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-extern bool arc_need_delay (rtx_insn *insn);
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extern bool arc_text_label (rtx_insn *insn);
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extern bool arc_short_comparison_p (rtx, int);
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diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
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index 5a7b0cb6696..c3ee9181f93 100644
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--- a/gcc/config/arc/arc.c
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+++ b/gcc/config/arc/arc.c
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@@ -10341,59 +10341,6 @@ arc_attr_type (rtx_insn *insn)
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return get_attr_type (insn);
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}
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-/* Return true if insn sets the condition codes. */
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-
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-bool
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-arc_sets_cc_p (rtx_insn *insn)
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-{
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- if (NONJUMP_INSN_P (insn))
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- if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
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- insn = seq->insn (seq->len () - 1);
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- return arc_attr_type (insn) == TYPE_COMPARE;
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-}
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-
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-/* Return true if INSN is an instruction with a delay slot we may want
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- to fill. */
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-
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-bool
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-arc_need_delay (rtx_insn *insn)
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-{
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- rtx_insn *next;
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-
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- if (!flag_delayed_branch)
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- return false;
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- /* The return at the end of a function needs a delay slot. */
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- if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
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- && (!(next = next_active_insn (insn))
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- || ((!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) != SEQUENCE)
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- && arc_attr_type (next) == TYPE_RETURN))
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- && (!TARGET_PAD_RETURN
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- || (prev_active_insn (insn)
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- && prev_active_insn (prev_active_insn (insn))
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- && prev_active_insn (prev_active_insn (prev_active_insn (insn))))))
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- return true;
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- if (NONJUMP_INSN_P (insn)
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- ? (GET_CODE (PATTERN (insn)) == USE
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- || GET_CODE (PATTERN (insn)) == CLOBBER
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- || GET_CODE (PATTERN (insn)) == SEQUENCE)
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- : JUMP_P (insn)
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- ? (GET_CODE (PATTERN (insn)) == ADDR_VEC
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- || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
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- : !CALL_P (insn))
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- return false;
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- return num_delay_slots (insn) != 0;
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-}
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-
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-/* Return true if the scheduling pass(es) has/have already run,
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- i.e. where possible, we should try to mitigate high latencies
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- by different instruction selection. */
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-
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-bool
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-arc_scheduling_not_expected (void)
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-{
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- return cfun->machine->arc_reorg_started;
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-}
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-
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/* Code has a minimum p2 alignment of 1, which we must restore after
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an ADDR_DIFF_VEC. */
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diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
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index f91adbc0d94..c635b69ddd5 100644
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--- a/gcc/config/arc/arc.md
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+++ b/gcc/config/arc/arc.md
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@@ -2847,43 +2847,25 @@ archs4x, archs4xd"
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(set_attr "type" "compare")
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(set_attr "length" "4,4,8")])
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-; w/c/c comes first (rather than w/0/C_0) to prevent the middle-end
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-; needlessly prioritizing the matching constraint.
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-; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional
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-; execution is used where possible.
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-(define_insn_and_split "adc"
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- [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w")
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- (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0))
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- (match_operand:SI 1 "nonmemory_operand"
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- "%c,0,c,0,cCal"))
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- (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))]
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+(define_insn "adc"
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+ [(set (match_operand:SI 0 "register_operand" "=r, r,r,r, r,r")
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+ (plus:SI
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+ (plus:SI
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+ (ltu:SI (reg:CC_C CC_REG) (const_int 0))
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+ (match_operand:SI 1 "nonmemory_operand" "%r, 0,r,0,Cal,r"))
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+ (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I, r,Cal")))]
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"register_operand (operands[1], SImode)
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|| register_operand (operands[2], SImode)"
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"@
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- adc %0,%1,%2
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- add.cs %0,%1,1
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- adc %0,%1,%2
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- adc %0,%1,%2
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- adc %0,%1,%2"
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- ; if we have a bad schedule after sched2, split.
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- "reload_completed
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- && !optimize_size && (!TARGET_ARC600_FAMILY)
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- && arc_scheduling_not_expected ()
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- && arc_sets_cc_p (prev_nonnote_insn (insn))
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- /* If next comes a return or other insn that needs a delay slot,
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- expect the adc to get into the delay slot. */
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- && next_nonnote_insn (insn)
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- && !arc_need_delay (next_nonnote_insn (insn))
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- /* Restore operands before emitting. */
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- && (extract_insn_cached (insn), 1)"
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- [(set (match_dup 0) (match_dup 3))
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- (cond_exec
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- (ltu (reg:CC_C CC_REG) (const_int 0))
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- (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))))]
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- "operands[3] = simplify_gen_binary (PLUS, SImode, operands[1], operands[2]);"
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+ adc\\t%0,%1,%2
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+ add.cs\\t%0,%1,1
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+ adc\\t%0,%1,%2
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+ adc\\t%0,%1,%2
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+ adc\\t%0,%1,%2
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+ adc\\t%0,%1,%2"
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[(set_attr "cond" "use")
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(set_attr "type" "cc_arith")
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- (set_attr "length" "4,4,4,4,8")])
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+ (set_attr "length" "4,4,4,4,8,8")])
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; combiner-splitter cmp / scc -> cmp / adc
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(define_split
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@@ -3015,7 +2997,7 @@ archs4x, archs4xd"
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DONE;
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}
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emit_insn (gen_sub_f (l0, l1, l2));
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- emit_insn (gen_sbc (h0, h1, h2, gen_rtx_REG (CCmode, CC_REG)));
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+ emit_insn (gen_sbc (h0, h1, h2));
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DONE;
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")
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@@ -3030,44 +3012,25 @@ archs4x, archs4xd"
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(set_attr "type" "cc_arith")
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(set_attr "length" "4")])
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-; w/c/c comes first (rather than Rcw/0/C_0) to prevent the middle-end
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-; needlessly prioritizing the matching constraint.
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-; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional execution
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-; is used where possible.
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-(define_insn_and_split "sbc"
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- [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w")
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- (minus:SI (minus:SI (match_operand:SI 1 "nonmemory_operand"
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- "c,0,c,0,cCal")
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- (ltu:SI (match_operand:CC_C 3 "cc_use_register")
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- (const_int 0)))
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- (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))]
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+(define_insn "sbc"
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+ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r,r,r,r")
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+ (minus:SI
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+ (minus:SI
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+ (match_operand:SI 1 "nonmemory_operand" "r, 0,r,0, r,Cal")
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+ (ltu:SI (reg:CC_C CC_REG) (const_int 0)))
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+ (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I,Cal,r")))]
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"register_operand (operands[1], SImode)
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|| register_operand (operands[2], SImode)"
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"@
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- sbc %0,%1,%2
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- sub.cs %0,%1,1
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- sbc %0,%1,%2
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- sbc %0,%1,%2
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- sbc %0,%1,%2"
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- ; if we have a bad schedule after sched2, split.
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- "reload_completed
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- && !optimize_size && (!TARGET_ARC600_FAMILY)
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- && arc_scheduling_not_expected ()
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- && arc_sets_cc_p (prev_nonnote_insn (insn))
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- /* If next comes a return or other insn that needs a delay slot,
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- expect the adc to get into the delay slot. */
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- && next_nonnote_insn (insn)
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- && !arc_need_delay (next_nonnote_insn (insn))
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- /* Restore operands before emitting. */
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- && (extract_insn_cached (insn), 1)"
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- [(set (match_dup 0) (match_dup 4))
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- (cond_exec
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- (ltu (reg:CC_C CC_REG) (const_int 0))
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- (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1))))]
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- "operands[4] = simplify_gen_binary (MINUS, SImode, operands[1], operands[2]);"
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+ sbc\\t%0,%1,%2
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+ sub.cs\\t%0,%1,1
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+ sbc\\t%0,%1,%2
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+ sbc\\t%0,%1,%2
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+ sbc\\t%0,%1,%2
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+ sbc\\t%0,%1,%2"
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[(set_attr "cond" "use")
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(set_attr "type" "cc_arith")
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- (set_attr "length" "4,4,4,4,8")])
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+ (set_attr "length" "4,4,4,4,8,8")])
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(define_insn "sub_f"
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[(set (reg:CC CC_REG)
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