/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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/*
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* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
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*/
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unsigned long get_board_sys_clk(ulong dummy)
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{
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#if defined(CONFIG_MPC85xx)
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#elif defined(CONFIG_MPC86xx)
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immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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#endif
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if (in_be32(&gur->gpporcr) & 0x10000)
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return 66666666;
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else
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#ifdef CONFIG_ARCH_P2020
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return 100000000;
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#else
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return 50000000;
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#endif
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}
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#ifdef CONFIG_MPC85xx
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/*
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* Return DDR input clock - synchronous with SYSCLK or 66 MHz
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* Note: 86xx doesn't support asynchronous DDR clk
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*/
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
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if (ddr_ratio == 0x7)
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return get_board_sys_clk(dummy);
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#ifdef CONFIG_ARCH_P2020
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if (in_be32(&gur->gpporcr) & 0x20000)
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return 66666666;
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else
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return 100000000;
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#else
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return 66666666;
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#endif
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}
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#endif
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