/*
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* Embest/Timll DevKit3250 board support
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*
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* Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/emc.h>
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#include <asm/arch/wdt.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
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void reset_periph(void)
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{
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/* This function resets peripherals by triggering RESOUT_N */
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setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
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writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
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udelay(300);
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writel(0, &wdt->mctrl);
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clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
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/* Such a long delay is needed to initialize SMSC phy */
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udelay(10000);
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}
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int board_early_init_f(void)
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{
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lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
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lpc32xx_i2c_init(1);
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lpc32xx_i2c_init(2);
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lpc32xx_ssp_init();
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lpc32xx_mac_init();
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/*
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* nWP may be controlled by GPO19, but unpopulated by default R23
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* makes no sense to configure this GPIO level, nWP is always high
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*/
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lpc32xx_slc_nand_init();
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_SYS_FLASH_CFI
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/* Use 16-bit memory interface for NOR Flash */
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emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
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/* Change the NOR timings to optimum value to get maximum bandwidth */
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emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
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emc->stat[0].waitoen = EMC_STAT_WAITOEN(0);
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emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
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emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
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emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
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emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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