/*
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* Copyright (C) 2007,2008 Nobuhiro Iwamatsu
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*
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* u-boot/board/r7780mp/lowlevel_init.S
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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/*
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* Board specific low level init code, called _very_ early in the
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* startup sequence. Relocation to SDRAM has not happened yet, no
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* stack is available, bss section has not been initialised, etc.
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*
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* (Note: As no stack is available, no subroutines can be called...).
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*/
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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write32 CCR_A, CCR_D /* Address of Cache Control Register */
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/* Instruction Cache Invalidate */
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write32 FRQCR_A, FRQCR_D /* Frequency control register */
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/* pin_multi_setting */
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write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
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write32 BBG_PMSR1_A, BBG_PMSR1_D
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write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
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write32 BBG_PMSR2_A, BBG_PMSR2_D
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write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
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write32 BBG_PMSR3_A, BBG_PMSR3_D
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write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
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write32 BBG_PMSR4_A, BBG_PMSR4_D
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write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
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write32 BBG_PMSRG_A, BBG_PMSRG_D
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/* cpg_setting */
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write32 FRQCR_A, FRQCR_D
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write32 DLLCSR_A, DLLCSR_D
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/* wait 200us */
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mov.l REPEAT0_R3, r3
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mov #0, r2
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repeat0:
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add #1, r2
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cmp/hs r3, r2
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bf repeat0
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nop
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/* bsc_setting */
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write32 MMSELR_A, MMSELR_D
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write32 BCR_A, BCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS1BCR_A, CS1BCR_D
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write32 CS2BCR_A, CS2BCR_D
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write32 CS4BCR_A, CS4BCR_D
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write32 CS5BCR_A, CS5BCR_D
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write32 CS6BCR_A, CS6BCR_D
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write32 CS0WCR_A, CS0WCR_D
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write32 CS1WCR_A, CS1WCR_D
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write32 CS2WCR_A, CS2WCR_D
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write32 CS4WCR_A, CS4WCR_D
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write32 CS5WCR_A, CS5WCR_D
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write32 CS6WCR_A, CS6WCR_D
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write32 CS5PCR_A, CS5PCR_D
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write32 CS6PCR_A, CS6PCR_D
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/* ddr_setting */
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/* wait 200us */
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mov.l REPEAT0_R3, r3
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mov #0, r2
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repeat1:
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add #1, r2
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cmp/hs r3, r2
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bf repeat1
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nop
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mov.l MIM_U_A, r0
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mov.l MIM_U_D, r1
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synco
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mov.l r1, @r0
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synco
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mov.l MIM_L_A, r0
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mov.l MIM_L_D0, r1
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synco
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mov.l r1, @r0
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synco
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mov.l STR_L_A, r0
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mov.l STR_L_D, r1
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synco
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mov.l r1, @r0
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synco
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mov.l SDR_L_A, r0
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mov.l SDR_L_D, r1
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synco
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mov.l r1, @r0
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synco
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nop
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nop
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nop
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nop
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mov.l SCR_L_A, r0
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mov.l SCR_L_D0, r1
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synco
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mov.l r1, @r0
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synco
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mov.l SCR_L_A, r0
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mov.l SCR_L_D1, r1
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synco
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mov.l r1, @r0
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synco
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nop
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nop
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nop
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mov.l EMRS_A, r0
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mov.l EMRS_D, r1
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synco
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mov.l r1, @r0
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synco
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nop
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nop
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nop
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mov.l MRS1_A, r0
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mov.l MRS1_D, r1
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synco
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mov.l r1, @r0
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synco
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nop
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nop
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nop
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mov.l SCR_L_A, r0
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mov.l SCR_L_D2, r1
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synco
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mov.l r1, @r0
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synco
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nop
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nop
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nop
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mov.l SCR_L_A, r0
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mov.l SCR_L_D3, r1
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synco
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mov.l r1, @r0
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synco
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nop
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nop
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nop
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mov.l SCR_L_A, r0
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mov.l SCR_L_D4, r1
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synco
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mov.l r1, @r0
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synco
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nop
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nop
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nop
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mov.l MRS2_A, r0
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mov.l MRS2_D, r1
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synco
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mov.l r1, @r0
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synco
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nop
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nop
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nop
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mov.l SCR_L_A, r0
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mov.l SCR_L_D5, r1
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synco
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mov.l r1, @r0
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synco
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/* wait 200us */
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mov.l REPEAT0_R1, r3
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mov #0, r2
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repeat2:
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add #1, r2
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cmp/hs r3, r2
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bf repeat2
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synco
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mov.l MIM_L_A, r0
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mov.l MIM_L_D1, r1
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synco
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mov.l r1, @r0
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synco
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rts
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nop
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.align 4
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RWTCSR_D_1: .word 0xA507
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RWTCSR_D_2: .word 0xA507
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RWTCNT_D: .word 0x5A00
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.align 2
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BBG_PMMR_A: .long 0xFF800010
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BBG_PMSR1_A: .long 0xFF800014
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BBG_PMSR2_A: .long 0xFF800018
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BBG_PMSR3_A: .long 0xFF80001C
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BBG_PMSR4_A: .long 0xFF800020
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BBG_PMSRG_A: .long 0xFF800024
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BBG_PMMR_D_PMSR1: .long 0xffffbffd
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BBG_PMSR1_D: .long 0x00004002
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BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
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BBG_PMSR2_D: .long 0x03de5800
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BBG_PMMR_D_PMSR3: .long 0xfffffff8
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BBG_PMSR3_D: .long 0x00000007
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BBG_PMMR_D_PMSR4: .long 0xdffdfff9
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BBG_PMSR4_D: .long 0x20020006
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BBG_PMMR_D_PMSRG: .long 0xffffffff
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BBG_PMSRG_D: .long 0x00000000
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FRQCR_A: .long FRQCR
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DLLCSR_A: .long 0xffc40010
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FRQCR_D: .long 0x40233035
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DLLCSR_D: .long 0x00000000
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/* for DDR-SDRAM */
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MIM_U_A: .long MIM_1
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MIM_L_A: .long MIM_2
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SCR_U_A: .long SCR_1
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SCR_L_A: .long SCR_2
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STR_U_A: .long STR_1
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STR_L_A: .long STR_2
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SDR_U_A: .long SDR_1
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SDR_L_A: .long SDR_2
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EMRS_A: .long 0xFEC02000
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MRS1_A: .long 0xFEC00B08
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MRS2_A: .long 0xFEC00308
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MIM_U_D: .long 0x00004000
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MIM_L_D0: .long 0x03e80009
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MIM_L_D1: .long 0x03e80209
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SCR_L_D0: .long 0x3
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SCR_L_D1: .long 0x2
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SCR_L_D2: .long 0x2
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SCR_L_D3: .long 0x4
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SCR_L_D4: .long 0x4
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SCR_L_D5: .long 0x0
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STR_L_D: .long 0x000f0000
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SDR_L_D: .long 0x00000400
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EMRS_D: .long 0x0
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MRS1_D: .long 0x0
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MRS2_D: .long 0x0
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/* Cache Controller */
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CCR_A: .long CCR
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MMUCR_A: .long MMUCR
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RWTCNT_A: .long WTCNT
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CCR_D: .long 0x0000090b
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CCR_D_2: .long 0x00000103
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MMUCR_D: .long 0x00000004
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MSTPCR0_D: .long 0x00001001
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MSTPCR2_D: .long 0xffffffff
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/* local Bus State Controller */
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MMSELR_A: .long MMSELR
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BCR_A: .long BCR
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CS0BCR_A: .long CS0BCR
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CS1BCR_A: .long CS1BCR
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CS2BCR_A: .long CS2BCR
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CS4BCR_A: .long CS4BCR
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CS5BCR_A: .long CS5BCR
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CS6BCR_A: .long CS6BCR
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CS0WCR_A: .long CS0WCR
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CS1WCR_A: .long CS1WCR
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CS2WCR_A: .long CS2WCR
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CS4WCR_A: .long CS4WCR
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CS5WCR_A: .long CS5WCR
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CS6WCR_A: .long CS6WCR
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CS5PCR_A: .long CS5PCR
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CS6PCR_A: .long CS6PCR
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MMSELR_D: .long 0xA5A50003
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BCR_D: .long 0x00000000
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CS0BCR_D: .long 0x77777770
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CS1BCR_D: .long 0x77777670
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CS2BCR_D: .long 0x77777770
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CS4BCR_D: .long 0x77777770
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CS5BCR_D: .long 0x77777670
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CS6BCR_D: .long 0x77777770
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CS0WCR_D: .long 0x00020006
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CS1WCR_D: .long 0x00232304
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CS2WCR_D: .long 0x7777770F
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CS4WCR_D: .long 0x7777770F
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CS5WCR_D: .long 0x00101006
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CS6WCR_D: .long 0x77777703
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CS5PCR_D: .long 0x77000000
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CS6PCR_D: .long 0x77000000
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REPEAT0_R3: .long 0x00002000
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REPEAT0_R1: .long 0x0000200
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