/*
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* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include "vct.h"
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/*
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* Find out to which of the 2 gpio modules the pin specified in the
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* argument belongs:
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* GPIO_MODULE yields 0 for pins 0 to 31,
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* 1 for pins 32 to 63
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*/
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#define GPIO_MODULE(pin) ((pin) >> 5)
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/*
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* Bit position within a 32-bit peripheral register (where every
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* bit is one bitslice)
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*/
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#define MASK(pin) (1 << ((pin) & 0x1F))
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#define BASE_ADDR(mod) module_base[mod]
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/*
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* Lookup table for transforming gpio module number 0 to 2 to
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* address offsets
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*/
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static u32 module_base[] = {
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GPIO1_BASE,
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GPIO2_BASE
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};
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static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask)
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{
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reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask);
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}
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int vct_gpio_dir(int pin, int dir)
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{
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u32 gpio_base;
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gpio_base = BASE_ADDR(GPIO_MODULE(pin));
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if (dir == 0)
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clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0);
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else
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clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin));
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return 0;
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}
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void vct_gpio_set(int pin, int val)
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{
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u32 gpio_base;
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gpio_base = BASE_ADDR(GPIO_MODULE(pin));
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if (val == 0)
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clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0);
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else
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clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin));
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}
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int vct_gpio_get(int pin)
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{
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u32 gpio_base;
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u32 value;
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gpio_base = BASE_ADDR(GPIO_MODULE(pin));
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value = reg_read(GPIO_EXT_PORTA(gpio_base));
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return ((value & MASK(pin)) ? 1 : 0);
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}
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