/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
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#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
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#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
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#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
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#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
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#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
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#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
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#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
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#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
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#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
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#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
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#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
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#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
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#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
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#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
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#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
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#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
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#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
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#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
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#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
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#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
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#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
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#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
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#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
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#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
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#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
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#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
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#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
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#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
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#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
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#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
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#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
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#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
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#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
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#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
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#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
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#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
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#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
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#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
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#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
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#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
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#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
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#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
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#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
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#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_TIMING_4 0x00000001
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#define CONFIG_SYS_DDR_TIMING_5 0x02401400
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
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#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
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#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
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.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
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.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
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.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
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.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
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.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
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.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
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.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
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.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
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.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
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.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fixed_ddr_parm_t fixed_ddr_parm_0[] = {
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{750, 850, &ddr_cfg_regs_800},
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{850, 950, &ddr_cfg_regs_900},
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{950, 1050, &ddr_cfg_regs_1000},
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{1050, 1250, &ddr_cfg_regs_1200},
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{0, 0, NULL}
|
};
|
|
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
|
{750, 850, &ddr_cfg_regs_800_2nd},
|
{850, 950, &ddr_cfg_regs_900_2nd},
|
{950, 1050, &ddr_cfg_regs_1000_2nd},
|
{1050, 1250, &ddr_cfg_regs_1200_2nd},
|
{0, 0, NULL}
|
};
|
