/*
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* Copyright 2004, 2011 Freescale Semiconductor.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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/*
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* CADMUS Board System Registers
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*/
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#ifndef CONFIG_SYS_CADMUS_BASE_REG
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#define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
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#endif
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typedef struct cadmus_reg {
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u_char cm_ver; /* Board version */
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u_char cm_csr; /* General control/status */
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u_char cm_rst; /* Reset control */
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u_char cm_hsclk; /* High speed clock */
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u_char cm_hsxclk; /* High speed clock extended */
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u_char cm_led; /* LED data */
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u_char cm_pci; /* PCI control/status */
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u_char cm_dma; /* DMA control */
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u_char cm_reserved[248]; /* Total 256 bytes */
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} cadmus_reg_t;
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unsigned int
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get_board_version(void)
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{
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volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
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return cadmus->cm_ver;
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}
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unsigned long
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get_clock_freq(void)
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{
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volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
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uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
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if (pci1_speed == 0) {
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return 33333333;
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} else if (pci1_speed == 1) {
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return 66666666;
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} else {
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/* Really, unknown. Be safe? */
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return 33333333;
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}
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}
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unsigned int
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get_pci_slot(void)
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{
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volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
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/*
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* PCI slot in USER bits CSR[6:7] by convention.
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*/
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return ((cadmus->cm_csr >> 6) & 0x3) + 1;
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}
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unsigned int
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get_pci_dual(void)
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{
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volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
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/*
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* PCI DUAL in CM_PCI[3]
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*/
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return cadmus->cm_pci & 0x10;
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}
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