/**
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* Copyright 2013 Freescale Semiconductor
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* Author: Mingkai Hu <Mingkai.Hu@freescale.com>
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* Po Liu <Po.Liu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* This file provides support for the ngPIXIS, a board-specific FPGA used on
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* some Freescale reference boards.
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*/
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/*
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* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
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*/
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struct cpld_data {
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u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */
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u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */
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u8 hwver; /* 0x2 - Hardware Version Register */
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u8 cpldver; /* 0x3 - Software Version Register */
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u8 res[12];
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u8 rstcon; /* 0x10 - Reset control register */
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u8 flhcsr; /* 0x11 - Flash control and status Register */
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u8 wdcsr; /* 0x12 - Watchdog control and status Register */
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u8 wdkick; /* 0x13 - Watchdog kick Register */
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u8 fancsr; /* 0x14 - Fan control and status Register */
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u8 ledcsr; /* 0x15 - LED control and status Register */
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u8 misccsr; /* 0x16 - Misc control and status Register */
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u8 bootor; /* 0x17 - Boot configure override Register */
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u8 bootcfg1; /* 0x18 - Boot configure 1 Register */
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u8 bootcfg2; /* 0x19 - Boot configure 2 Register */
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u8 bootcfg3; /* 0x1a - Boot configure 3 Register */
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u8 bootcfg4; /* 0x1b - Boot configure 4 Register */
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};
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#define CPLD_BANKSEL_EN 0x02
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#define CPLD_BANKSEL_MASK 0x3f
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#define CPLD_SELECT_BANK1 0xc0
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#define CPLD_SELECT_BANK2 0x80
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#define CPLD_SELECT_BANK3 0x40
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#define CPLD_SELECT_BANK4 0x00
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