/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __ASM_ARCH_PCH_H
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#define __ASM_ARCH_PCH_H
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/* CPU bus clock is fixed at 100MHz */
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#define CPU_BCLK 100
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#define PMBASE 0x40
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#define ACPI_CNTL 0x44
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#define ACPI_EN (1 << 7)
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#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
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#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
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#define GPIO_EN (1 << 4)
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#define PCIEXBAR 0x60
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#define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0)
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/* RCB registers */
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#define OIC 0x31fe /* 16bit */
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#define HPTC 0x3404 /* 32bit */
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#define FD 0x3418 /* 32bit */
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/* Function Disable 1 RCBA 0x3418 */
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#define PCH_DISABLE_ALWAYS (1 << 0)
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/* PM registers */
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#define TCO1_CNT 0x60
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#define TCO_TMR_HLT (1 << 11)
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/* Device 0:0.0 PCI configuration space */
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#define EPBAR 0x40
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#define MCHBAR 0x48
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#define PCIEXBAR 0x60
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#define DMIBAR 0x68
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#define GGC 0x50 /* GMCH Graphics Control */
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#define DEVEN 0x54 /* Device Enable */
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#define DEVEN_D7EN (1 << 14)
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#define DEVEN_D4EN (1 << 7)
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#define DEVEN_D3EN (1 << 5)
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#define DEVEN_D2EN (1 << 4)
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#define DEVEN_D1F0EN (1 << 3)
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#define DEVEN_D1F1EN (1 << 2)
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#define DEVEN_D1F2EN (1 << 1)
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#define DEVEN_D0EN (1 << 0)
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#define DPR 0x5c
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#define DPR_EPM (1 << 2)
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#define DPR_PRS (1 << 1)
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#define DPR_SIZE_MASK 0xff0
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#define MCHBAR_PEI_VERSION 0x5034
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#define BIOS_RESET_CPL 0x5da8
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#define EDRAMBAR 0x5408
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#define MCH_PAIR 0x5418
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#define GDXCBAR 0x5420
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#define PAM0 0x80
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#define PAM1 0x81
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#define PAM2 0x82
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#define PAM3 0x83
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#define PAM4 0x84
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#define PAM5 0x85
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#define PAM6 0x86
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/* PCODE MMIO communications live in the MCHBAR. */
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#define BIOS_MAILBOX_INTERFACE 0x5da4
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#define MAILBOX_RUN_BUSY (1 << 31)
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#define MAILBOX_BIOS_CMD_READ_PCS 1
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#define MAILBOX_BIOS_CMD_WRITE_PCS 2
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#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509
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#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909
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#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa
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#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb
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#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26
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#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27
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/* Errors are returned back in bits 7:0. */
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#define MAILBOX_BIOS_ERROR_NONE 0
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#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
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#define MAILBOX_BIOS_ERROR_TIMEOUT 2
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#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3
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#define MAILBOX_BIOS_ERROR_RESERVED 4
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#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
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#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
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#define MAILBOX_BIOS_ERROR_VR_ERROR 7
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/* Data is passed through bits 31:0 of the data register. */
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#define BIOS_MAILBOX_DATA 0x5da0
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/* SATA IOBP Registers */
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#define SATA_IOBP_SP0_SECRT88 0xea002688
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#define SATA_IOBP_SP1_SECRT88 0xea002488
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#define SATA_SECRT88_VADJ_MASK 0xff
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#define SATA_SECRT88_VADJ_SHIFT 16
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#define SATA_IOBP_SP0DTLE_DATA 0xea002550
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#define SATA_IOBP_SP0DTLE_EDGE 0xea002554
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#define SATA_IOBP_SP1DTLE_DATA 0xea002750
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#define SATA_IOBP_SP1DTLE_EDGE 0xea002754
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#define SATA_DTLE_MASK 0xF
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#define SATA_DTLE_DATA_SHIFT 24
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#define SATA_DTLE_EDGE_SHIFT 16
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/* Power Management */
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#define GEN_PMCON_1 0xa0
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#define SMI_LOCK (1 << 4)
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#define GEN_PMCON_2 0xa2
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#define SYSTEM_RESET_STS (1 << 4)
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#define THERMTRIP_STS (1 << 3)
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#define SYSPWR_FLR (1 << 1)
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#define PWROK_FLR (1 << 0)
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#define GEN_PMCON_3 0xa4
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#define SUS_PWR_FLR (1 << 14)
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#define GEN_RST_STS (1 << 9)
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#define RTC_BATTERY_DEAD (1 << 2)
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#define PWR_FLR (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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#define GEN_PMCON_LOCK 0xa6
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#define SLP_STR_POL_LOCK (1 << 2)
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#define ACPI_BASE_LOCK (1 << 1)
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#define PMIR 0xac
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#define PMIR_CF9LOCK (1 << 31)
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#define PMIR_CF9GR (1 << 20)
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/* Broadwell PCH (Wildcat Point) */
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#define PCH_WPT_HSW_U_SAMPLE 0x9cc1
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#define PCH_WPT_BDW_U_SAMPLE 0x9cc2
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#define PCH_WPT_BDW_U_PREMIUM 0x9cc3
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#define PCH_WPT_BDW_U_BASE 0x9cc5
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#define PCH_WPT_BDW_Y_SAMPLE 0x9cc6
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#define PCH_WPT_BDW_Y_PREMIUM 0x9cc7
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#define PCH_WPT_BDW_Y_BASE 0x9cc9
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#define PCH_WPT_BDW_H 0x9ccb
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#define SA_IGD_OPROM_VENDEV 0x80860406
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/* Dynamically determine if the part is ULT */
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bool cpu_is_ult(void);
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u32 pch_iobp_read(u32 address);
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int pch_iobp_write(u32 address, u32 data);
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int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
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int pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
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#endif
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