/*
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* From coreboot soc/intel/broadwell/include/soc/lpc.h
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*
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* Copyright (C) 2016 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_ARCH_LPC_H
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#define _ASM_ARCH_LPC_H
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#define GEN_PMCON_1 0xa0
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#define SMI_LOCK (1 << 4)
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#define GEN_PMCON_2 0xa2
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#define SYSTEM_RESET_STS (1 << 4)
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#define THERMTRIP_STS (1 << 3)
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#define SYSPWR_FLR (1 << 1)
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#define PWROK_FLR (1 << 0)
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#define GEN_PMCON_3 0xa4
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#define SUS_PWR_FLR (1 << 14)
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#define GEN_RST_STS (1 << 9)
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#define RTC_BATTERY_DEAD (1 << 2)
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#define PWR_FLR (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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#define GEN_PMCON_LOCK 0xa6
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#define SLP_STR_POL_LOCK (1 << 2)
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#define ACPI_BASE_LOCK (1 << 1)
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#define PMIR 0xac
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#define PMIR_CF9LOCK (1 << 31)
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#define PMIR_CF9GR (1 << 20)
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#endif
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