/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Ported from Intel released Quark UEFI BIOS
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* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
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*
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* SPDX-License-Identifier: Intel
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*/
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#ifndef _MRC_UTIL_H_
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#define _MRC_UTIL_H_
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/* Turn on this macro to enable MRC debugging output */
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#undef MRC_DEBUG
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/* MRC Debug Support */
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#define DPF debug_cond
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/* debug print type */
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#ifdef MRC_DEBUG
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#define D_ERROR 0x0001
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#define D_INFO 0x0002
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#define D_REGRD 0x0004
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#define D_REGWR 0x0008
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#define D_FCALL 0x0010
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#define D_TRN 0x0020
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#define D_TIME 0x0040
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#else
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#define D_ERROR 0
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#define D_INFO 0
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#define D_REGRD 0
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#define D_REGWR 0
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#define D_FCALL 0
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#define D_TRN 0
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#define D_TIME 0
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#endif
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#define ENTERFN(...) debug_cond(D_FCALL, "<%s>\n", __func__)
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#define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__)
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#define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__)
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/* Message Bus Port */
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#define MEM_CTLR 0x01
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#define HOST_BRIDGE 0x03
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#define MEM_MGR 0x05
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#define HTE 0x11
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#define DDRPHY 0x12
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/* number of sample points */
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#define SAMPLE_CNT 3
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/* number of PIs to increment per sample */
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#define SAMPLE_DLY 26
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enum {
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/* indicates to decrease delays when looking for edge */
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BACKWARD,
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/* indicates to increase delays when looking for edge */
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FORWARD
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};
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enum {
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RCVN,
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WDQS,
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WDQX,
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RDQS,
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VREF,
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WCMD,
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WCTL,
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WCLK,
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MAX_ALGOS,
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};
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void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
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void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
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void mrc_post_code(uint8_t major, uint8_t minor);
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void delay_n(uint32_t ns);
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void delay_u(uint32_t ms);
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void select_mem_mgr(void);
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void select_hte(void);
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void dram_init_command(uint32_t data);
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void dram_wake_command(void);
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void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane);
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void set_rcvn(uint8_t channel, uint8_t rank,
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uint8_t byte_lane, uint32_t pi_count);
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uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane);
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void set_rdqs(uint8_t channel, uint8_t rank,
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uint8_t byte_lane, uint32_t pi_count);
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uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
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void set_wdqs(uint8_t channel, uint8_t rank,
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uint8_t byte_lane, uint32_t pi_count);
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uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
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void set_wdq(uint8_t channel, uint8_t rank,
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uint8_t byte_lane, uint32_t pi_count);
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uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane);
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void set_wcmd(uint8_t channel, uint32_t pi_count);
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uint32_t get_wcmd(uint8_t channel);
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void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count);
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uint32_t get_wclk(uint8_t channel, uint8_t rank);
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void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count);
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uint32_t get_wctl(uint8_t channel, uint8_t rank);
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void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting);
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uint32_t get_vref(uint8_t channel, uint8_t byte_lane);
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uint32_t get_addr(uint8_t channel, uint8_t rank);
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uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
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uint8_t rank, bool rcvn);
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void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
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uint8_t channel, uint8_t rank, bool rcvn);
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uint32_t byte_lane_mask(struct mrc_params *mrc_params);
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uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address);
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uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address);
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void lfsr32(uint32_t *lfsr_ptr);
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void clear_pointers(void);
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void print_timings(struct mrc_params *mrc_params);
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#endif /* _MRC_UTIL_H_ */
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