/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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* Copyright (C) 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/irq.h>
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#include <asm/arch/device.h>
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#include <asm/arch/quark.h>
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int quark_irq_router_probe(struct udevice *dev)
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{
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struct quark_rcba *rcba;
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u32 base;
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qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
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base &= ~MEM_BAR_EN;
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rcba = (struct quark_rcba *)base;
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/*
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* Route Quark PCI device interrupt pin to PIRQ
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*
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* Route device#23's INTA/B/C/D to PIRQA/B/C/D
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* Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
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*/
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writew(PIRQC, &rcba->rmu_ir);
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writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
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&rcba->d23_ir);
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writew(PIRQD, &rcba->core_ir);
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writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
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&rcba->d20d21_ir);
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return irq_router_common_init(dev);
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}
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static const struct udevice_id quark_irq_router_ids[] = {
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{ .compatible = "intel,quark-irq-router" },
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{ }
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};
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U_BOOT_DRIVER(quark_irq_router_drv) = {
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.name = "quark_intel_irq",
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.id = UCLASS_IRQ,
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.of_match = quark_irq_router_ids,
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.probe = quark_irq_router_probe,
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};
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