/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* U-Boot - Startup Code for PowerPC based Embedded Boards
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*
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*
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* The processor starts at 0x00000100 and the code is executed
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* from flash. The code is organized to be at an other address
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* in memory, but as long we don't jump around before relocating,
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* board_init lies at a quite high address and when the cpu has
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* jumped there, everything is ok.
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* This works because the cpu gives the FLASH (CS0) the whole
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* address space at startup, and board_init lies as a echo of
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* the flash somewhere up there in the memory map.
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*
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* board_init will change CS0 to be positioned at the correct
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* address and (s)dram will be positioned at address 0
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <mpc8xx.h>
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#include <version.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <asm/u-boot.h>
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/* We don't want the MMU yet.
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*/
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#undef MSR_KERNEL
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#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
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/*
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* Set up GOT: Global Offset Table
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*
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* Use r12 to access the GOT
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*/
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START_GOT
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GOT_ENTRY(_GOT2_TABLE_)
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GOT_ENTRY(_FIXUP_TABLE_)
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GOT_ENTRY(_start)
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GOT_ENTRY(_start_of_vectors)
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GOT_ENTRY(_end_of_vectors)
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GOT_ENTRY(transfer_to_handler)
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GOT_ENTRY(__init_end)
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GOT_ENTRY(__bss_end)
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GOT_ENTRY(__bss_start)
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END_GOT
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/*
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* r3 - 1st arg to board_init(): IMMP pointer
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* r4 - 2nd arg to board_init(): boot flag
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*/
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.text
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.long 0x27051956 /* U-Boot Magic Number */
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.globl version_string
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version_string:
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.ascii U_BOOT_VERSION_STRING, "\0"
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. = EXC_OFF_SYS_RESET
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.globl _start
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_start:
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lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
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mtspr 638, r3
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/* Initialize machine status; enable machine check interrupt */
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/*----------------------------------------------------------------------*/
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li r3, MSR_KERNEL /* Set ME, RI flags */
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mtmsr r3
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mtspr SRR1, r3 /* Make SRR1 match MSR */
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mfspr r3, ICR /* clear Interrupt Cause Register */
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/* Initialize debug port registers */
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/*----------------------------------------------------------------------*/
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xor r0, r0, r0 /* Clear R0 */
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mtspr LCTRL1, r0 /* Initialize debug port regs */
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mtspr LCTRL2, r0
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mtspr COUNTA, r0
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mtspr COUNTB, r0
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/* Reset the caches */
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/*----------------------------------------------------------------------*/
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mfspr r3, IC_CST /* Clear error bits */
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mfspr r3, DC_CST
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lis r3, IDC_UNALL@h /* Unlock all */
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mtspr IC_CST, r3
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mtspr DC_CST, r3
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lis r3, IDC_INVALL@h /* Invalidate all */
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mtspr IC_CST, r3
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mtspr DC_CST, r3
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lis r3, IDC_DISABLE@h /* Disable data cache */
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mtspr DC_CST, r3
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lis r3, IDC_ENABLE@h /* Enable instruction cache */
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mtspr IC_CST, r3
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/* invalidate all tlb's */
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/*----------------------------------------------------------------------*/
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tlbia
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isync
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/*
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* Calculate absolute address in FLASH and jump there
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*----------------------------------------------------------------------*/
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lis r3, CONFIG_SYS_MONITOR_BASE@h
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ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
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addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
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mtlr r3
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blr
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in_flash:
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/* initialize some SPRs that are hard to access from C */
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/*----------------------------------------------------------------------*/
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lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */
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ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
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/* Note: R0 is still 0 here */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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/*
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* Disable serialized ifetch and show cycles
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* (i.e. set processor to normal mode).
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* This is also a silicon bug workaround, see errata
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*/
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li r2, 0x0007
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mtspr ICTRL, r2
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/* Set up debug mode entry */
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lis r2, CONFIG_SYS_DER@h
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ori r2, r2, CONFIG_SYS_DER@l
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mtspr DER, r2
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/* let the C-code set up the rest */
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/* */
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/* Be careful to keep code relocatable ! */
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/*----------------------------------------------------------------------*/
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GET_GOT /* initialize GOT access */
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/* r3: IMMR */
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bl cpu_init_f /* run low-level CPU init code (from Flash) */
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bl board_init_f /* run 1st part of board init code (from Flash) */
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/* NOTREACHED - board_init_f() does not return */
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.globl _start_of_vectors
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_start_of_vectors:
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/* Machine check */
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STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
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/* Data Storage exception. "Never" generated on the 860. */
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STD_EXCEPTION(0x300, DataStorage, UnknownException)
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/* Instruction Storage exception. "Never" generated on the 860. */
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STD_EXCEPTION(0x400, InstStorage, UnknownException)
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/* External Interrupt exception. */
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STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
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/* Alignment exception. */
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. = 0x600
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Alignment:
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EXCEPTION_PROLOG(SRR0, SRR1)
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mfspr r4,DAR
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stw r4,_DAR(r21)
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mfspr r5,DSISR
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stw r5,_DSISR(r21)
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
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/* Program check exception */
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. = 0x700
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ProgramCheck:
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EXCEPTION_PROLOG(SRR0, SRR1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
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MSR_KERNEL, COPY_EE)
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/* No FPU on MPC8xx. This exception is not supposed to happen.
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*/
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STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
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/* I guess we could implement decrementer, and may have
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* to someday for timekeeping.
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*/
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STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
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STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
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STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
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STD_EXCEPTION(0xc00, SystemCall, UnknownException)
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STD_EXCEPTION(0xd00, SingleStep, UnknownException)
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STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
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STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
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/* On the MPC8xx, this is a software emulation interrupt. It occurs
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* for all unimplemented and illegal instructions.
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*/
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STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
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STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
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STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
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STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
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STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
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STD_EXCEPTION(0x1500, Reserved5, UnknownException)
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STD_EXCEPTION(0x1600, Reserved6, UnknownException)
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STD_EXCEPTION(0x1700, Reserved7, UnknownException)
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STD_EXCEPTION(0x1800, Reserved8, UnknownException)
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STD_EXCEPTION(0x1900, Reserved9, UnknownException)
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STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
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STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
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STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
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STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
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STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
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STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
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.globl _end_of_vectors
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_end_of_vectors:
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. = 0x2000
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/*
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* This code finishes saving the registers to the exception frame
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* and jumps to the appropriate handler for the exception.
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* Register r21 is pointer into trap frame, r1 has new stack pointer.
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*/
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.globl transfer_to_handler
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transfer_to_handler:
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stw r22,_NIP(r21)
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lis r22,MSR_POW@h
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andc r23,r23,r22
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stw r23,_MSR(r21)
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SAVE_GPR(7, r21)
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SAVE_4GPRS(8, r21)
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SAVE_8GPRS(12, r21)
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SAVE_8GPRS(24, r21)
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mflr r23
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andi. r24,r23,0x3f00 /* get vector offset */
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stw r24,TRAP(r21)
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li r22,0
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stw r22,RESULT(r21)
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mtspr SPRG2,r22 /* r1 is now kernel sp */
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lwz r24,0(r23) /* virtual address of handler */
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lwz r23,4(r23) /* where to go when done */
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mtspr SRR0,r24
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mtspr SRR1,r20
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mtlr r23
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SYNC
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rfi /* jump to handler, enable MMU */
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int_return:
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mfmsr r28 /* Disable interrupts */
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li r4,0
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ori r4,r4,MSR_EE
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andc r28,r28,r4
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SYNC /* Some chip revs need this... */
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mtmsr r28
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SYNC
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lwz r2,_CTR(r1)
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lwz r0,_LINK(r1)
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mtctr r2
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mtlr r0
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lwz r2,_XER(r1)
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lwz r0,_CCR(r1)
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mtspr XER,r2
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mtcrf 0xFF,r0
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REST_10GPRS(3, r1)
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REST_10GPRS(13, r1)
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REST_8GPRS(23, r1)
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REST_GPR(31, r1)
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lwz r2,_NIP(r1) /* Restore environment */
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lwz r0,_MSR(r1)
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mtspr SRR0,r2
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mtspr SRR1,r0
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lwz r0,GPR0(r1)
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lwz r2,GPR2(r1)
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lwz r1,GPR1(r1)
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SYNC
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rfi
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/*------------------------------------------------------------------------------*/
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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* r3 = dest
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* r4 = src
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* r5 = length in bytes
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* r6 = cachelinesize
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*/
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.globl relocate_code
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relocate_code:
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mr r1, r3 /* Set new stack pointer */
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mr r9, r4 /* Save copy of Global Data pointer */
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mr r10, r5 /* Save copy of Destination Address */
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GET_GOT
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mr r3, r5 /* Destination Address */
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lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
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ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
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lwz r5, GOT(__init_end)
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sub r5, r5, r4
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li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
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/*
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* Fix GOT pointer:
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*
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* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
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*
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* Offset:
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*/
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sub r15, r10, r4
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/* First our own GOT */
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add r12, r12, r15
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/* then the one used by the C code */
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add r30, r30, r15
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/*
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* Now relocate code
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*/
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cmplw cr1,r3,r4
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addi r0,r5,3
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srwi. r0,r0,2
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beq cr1,4f /* In place copy is not necessary */
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beq 7f /* Protect against 0 count */
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mtctr r0
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bge cr1,2f
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la r8,-4(r4)
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la r7,-4(r3)
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1: lwzu r0,4(r8)
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stwu r0,4(r7)
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bdnz 1b
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b 4f
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2: slwi r0,r0,2
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add r8,r4,r0
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add r7,r3,r0
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3: lwzu r0,-4(r8)
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stwu r0,-4(r7)
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bdnz 3b
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/*
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* Now flush the cache: note that we must start from a cache aligned
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* address. Otherwise we might miss one cache line.
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*/
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4: cmpwi r6,0
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add r5,r3,r5
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beq 7f /* Always flush prefetch queue in any case */
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subi r0,r6,1
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andc r3,r3,r0
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mr r4,r3
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5: dcbst 0,r4
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add r4,r4,r6
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cmplw r4,r5
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blt 5b
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sync /* Wait for all dcbst to complete on bus */
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mr r4,r3
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6: icbi 0,r4
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add r4,r4,r6
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cmplw r4,r5
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blt 6b
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7: sync /* Wait for all icbi to complete on bus */
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isync
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
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mtlr r0
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blr
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in_ram:
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/*
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* Relocation Function, r12 point to got2+0x8000
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*
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* Adjust got2 pointers, no need to check for 0, this code
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* already puts a few entries in the table.
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*/
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li r0,__got2_entries@sectoff@l
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la r3,GOT(_GOT2_TABLE_)
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lwz r11,GOT(_GOT2_TABLE_)
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mtctr r0
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sub r11,r3,r11
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addi r3,r3,-4
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1: lwzu r0,4(r3)
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cmpwi r0,0
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beq- 2f
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add r0,r0,r11
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stw r0,0(r3)
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2: bdnz 1b
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/*
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* Now adjust the fixups and the pointers to the fixups
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* in case we need to move ourselves again.
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*/
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li r0,__fixup_entries@sectoff@l
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lwz r3,GOT(_FIXUP_TABLE_)
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cmpwi r0,0
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mtctr r0
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addi r3,r3,-4
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beq 4f
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3: lwzu r4,4(r3)
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lwzux r0,r4,r11
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cmpwi r0,0
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add r0,r0,r11
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stw r4,0(r3)
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beq- 5f
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stw r0,0(r4)
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5: bdnz 3b
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4:
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clear_bss:
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/*
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* Now clear BSS segment
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*/
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lwz r3,GOT(__bss_start)
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lwz r4,GOT(__bss_end)
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cmplw 0, r3, r4
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beq 6f
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li r0, 0
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5:
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stw r0, 0(r3)
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addi r3, r3, 4
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cmplw 0, r3, r4
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bne 5b
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6:
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mr r3, r9 /* Global Data pointer */
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mr r4, r10 /* Destination Address */
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bl board_init_r
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/*
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* Copy exception vector code to low memory
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*
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* r3: dest_addr
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* r7: source address, r8: end address, r9: target address
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*/
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.globl trap_init
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trap_init:
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mflr r4 /* save link register */
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GET_GOT
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lwz r7, GOT(_start)
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lwz r8, GOT(_end_of_vectors)
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li r9, 0x100 /* reset vector always at 0x100 */
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cmplw 0, r7, r8
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bgelr /* return if r7>=r8 - just in case */
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1:
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lwz r0, 0(r7)
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stw r0, 0(r9)
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addi r7, r7, 4
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addi r9, r9, 4
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cmplw 0, r7, r8
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bne 1b
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/*
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* relocate `hdlr' and `int_return' entries
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*/
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li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
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li r8, Alignment - _start + EXC_OFF_SYS_RESET
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2:
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bl trap_reloc
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addi r7, r7, 0x100 /* next exception vector */
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cmplw 0, r7, r8
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blt 2b
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li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
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bl trap_reloc
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li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
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bl trap_reloc
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li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
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li r8, SystemCall - _start + EXC_OFF_SYS_RESET
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3:
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bl trap_reloc
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addi r7, r7, 0x100 /* next exception vector */
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cmplw 0, r7, r8
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blt 3b
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li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
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li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
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4:
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bl trap_reloc
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addi r7, r7, 0x100 /* next exception vector */
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cmplw 0, r7, r8
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blt 4b
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mtlr r4 /* restore link register */
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blr
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