/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_NIOS2_CACHE_H_
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#define __ASM_NIOS2_CACHE_H_
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/*
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* Valid L1 data cache line sizes for the NIOS2 architecture are 4,
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* 16, and 32 bytes. We default to the largest of these values for
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* alignment of DMA buffers.
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*/
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#define ARCH_DMA_MINALIGN 32
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#endif /* __ASM_NIOS2_CACHE_H_ */
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