/*
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* Copyright (C) 2013-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc-regs.h"
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#undef DPLL_SSC_RATE_1PER
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int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
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{
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unsigned int dram_freq = bd->dram_freq;
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u32 tmp;
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/*
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* Set Frequency
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* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
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* to FOUT ( DPLLCTRL.bit[29:20] )
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*/
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tmp = readl(SC_DPLLCTRL);
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tmp &= ~(0x000f0000);
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switch (dram_freq) {
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case 1333:
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tmp |= 0x000d0000;
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break;
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case 1600:
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tmp |= 0x000c0000;
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break;
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default:
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pr_err("Unsupported frequency");
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return -EINVAL;
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}
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/*
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* Set Moduration rate
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* Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
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*/
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#if defined(DPLL_SSC_RATE_1PER)
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tmp &= ~0x00008000;
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#else
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tmp |= 0x00008000;
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#endif
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writel(tmp, SC_DPLLCTRL);
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tmp = readl(SC_DPLLCTRL2);
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tmp |= SC_DPLLCTRL2_NRSTDS;
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writel(tmp, SC_DPLLCTRL2);
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/* Wait until dpll gets stable */
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udelay(500);
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return 0;
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}
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