/*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/pmc.h>
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#include "../cpu.h"
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static void enable_cpu_power_rail(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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reg = readl(&pmc->pmc_cntrl);
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reg |= CPUPWRREQ_OE;
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writel(reg, &pmc->pmc_cntrl);
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/*
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* The TI PMU65861C needs a 3.75ms delay between enabling
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* the power rail and enabling the CPU clock. This delay
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* between SM1EN and SM1 is for switching time + the ramp
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* up of the voltage to the CPU (VDD_CPU from PMU).
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*/
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udelay(3750);
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}
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void start_cpu(u32 reset_vector)
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{
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/* Enable VDD_CPU */
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enable_cpu_power_rail();
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/* Hold the CPUs in reset */
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reset_A9_cpu(1);
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/* Disable the CPU clock */
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enable_cpu_clock(0);
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/* Enable CoreSight */
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clock_enable_coresight(1);
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/*
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* Set the entry point for CPU execution from reset,
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* if it's a non-zero value.
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*/
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if (reset_vector)
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writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
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/* Enable the CPU clock */
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enable_cpu_clock(1);
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/* If the CPU doesn't already have power, power it up */
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powerup_cpu();
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/* Take the CPU out of reset */
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reset_A9_cpu(0);
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}
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