@
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@ ARMv8 RMR reset sequence on Allwinner SoCs.
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@
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@ All 64-bit capable Allwinner SoCs reset in AArch32 (and continue to
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@ exectute the Boot ROM in this state), so we need to switch to AArch64
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@ at some point.
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@ Section G6.2.133 of the ARMv8 ARM describes the Reset Management Register
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@ (RMR), which triggers a warm-reset of a core and can request to switch
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@ into a different execution state (AArch32 or AArch64).
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@ The address at which execution starts after the reset is held in the
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@ RVBAR system register, which is architecturally read-only.
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@ Allwinner provides a writable alias of this register in MMIO space, so
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@ we can easily set the start address of AArch64 code.
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@ This code below switches to AArch64 and starts execution at the specified
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@ start address. It needs to be assembled by an ARM(32) assembler and
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@ the machine code must be inserted as verbatim .word statements into the
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@ beginning of the AArch64 U-Boot code.
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@ To get the encoded bytes, use:
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@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S
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@ ${CROSS_COMPILE}objdump -d rmr_switch.o
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@
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@ The resulting words should be inserted into the U-Boot file at
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@ arch/arm/include/asm/arch-sunxi/boot0.h.
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@
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@ This file is not build by the U-Boot build system, but provided only as a
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@ reference and to be able to regenerate a (probably fixed) version of this
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@ code found in encoded form in boot0.h.
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.text
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ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register
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ldr r0, =0x57aA7add @ start address, to be replaced
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str r0, [r1]
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dsb sy
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isb sy
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mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
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orr r0, r0, #3 @ request reset in AArch64
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mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
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isb sy
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1: wfi
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b 1b
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