/*
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* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <asm/arch/clock_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_clock_manager *clock_manager_base =
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(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
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void cm_wait_for_lock(u32 mask)
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{
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u32 inter_val;
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u32 retry = 0;
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do {
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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inter_val = readl(&clock_manager_base->inter) & mask;
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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inter_val = readl(&clock_manager_base->stat) & mask;
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#endif
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/* Wait for stable lock */
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if (inter_val == mask)
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retry++;
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else
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retry = 0;
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if (retry >= 10)
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break;
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} while (1);
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}
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/* function to poll in the fsm busy bit */
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int cm_wait_for_fsm(void)
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{
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return wait_for_bit_le32(&clock_manager_base->stat,
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CLKMGR_STAT_BUSY, false, 20000, false);
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}
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int set_cpu_clk_info(void)
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{
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/* Calculate the clock frequencies required for drivers */
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cm_get_l4_sp_clk_hz();
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cm_get_mmc_controller_clk_hz();
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gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
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gd->bd->bi_dsp_freq = 0;
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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gd->bd->bi_ddr_freq = 0;
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#endif
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return 0;
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}
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int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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cm_print_clock_quick_summary();
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return 0;
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}
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U_BOOT_CMD(
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clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
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"display clocks",
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""
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);
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