// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/ioc_rk3588.h>
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#include <dt-bindings/clock/rk3588-cru.h>
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#include <pci.h>
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#include <asm/arch/rk_atags.h>
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#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS
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#error "SPL_LOAD_FIT_ADDRESS not defined!"
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#endif
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#define printep(fmt, ...) \
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do { \
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printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \
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printf(fmt, ##__VA_ARGS__); \
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} while (0)
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#ifdef CONFIG_ROCKCHIP_RK3588
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#define PCIE_SNPS_DBI_BASE 0xf5000000
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#define PCIE_SNPS_APB_BASE 0xfe150000
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#define PCIE_SNPS_IATU_BASE 0xa40300000
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#define PCI_RESBAR 0x2e8
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#elif CONFIG_ROCKCHIP_RK3568
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#define PCIE_SNPS_DBI_BASE 0xf6000000
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#define PCIE_SNPS_APB_BASE 0xfe280000
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#define PCIE_SNPS_IATU_BASE 0x3c0b00000
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#define PCI_RESBAR 0x2b8
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#else
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#error "this soc is not support pcie ep!"
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#endif
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#define RKEP_BAR0_ADDR 0x3c000000
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#define RKEP_BAR2_ADDR CONFIG_SPL_LOAD_FIT_ADDRESS
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#define RKEP_BAR0_CMD_ADDR (RKEP_BAR0_ADDR + 0x400)
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#define RKEP_BOOT_MAGIC 0x524b4550 /* RKEP */
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#define RKEP_CMD_LOADER_RUN 0x524b4501
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#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
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#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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#define PCI_EXP_LNKCTL2_TLS 0x000f
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#define PCI_EXP_LNKCAP_SLS 0x0000000f
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#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
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/* Synopsys-specific PCIe configuration registers */
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#define PCIE_PORT_LINK_CONTROL 0x710
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#define PORT_LINK_MODE_MASK (0x3f << 16)
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#define PORT_LINK_MODE_1_LANES (0x1 << 16)
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#define PORT_LINK_MODE_2_LANES (0x3 << 16)
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#define PORT_LINK_MODE_4_LANES (0x7 << 16)
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#define PORT_LINK_MODE_8_LANES (0xf << 16)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
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#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
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#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
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#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
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#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
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#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
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#define PCIE_DIRECT_SPEED_CHANGE (0x1 << 17)
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#define LINK_WAIT_IATU 10000
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30 | 1 << 19)
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#define PCIE_ATU_UNR_REGION_CTRL1 0x00
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#define PCIE_ATU_UNR_REGION_CTRL2 0x04
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#define PCIE_ATU_CPU_ADDR_LOW 0x14
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#define PCIE_ATU_CPU_ADDR_HIGH 0x18
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/* SRNS: Use Separate refclk(internal clock) instead of from RC */
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// #define PCIE_ENABLE_SRNS_PLL_REFCLK
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struct rkpcie_cmd {
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u32 cmd;
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u32 size;
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u32 data[6];
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};
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/* rkep device mode status definition */
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#define RKEP_MODE_BOOTROM 1
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#define RKEP_MODE_LOADER 2
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#define RKEP_MODE_KERNEL 3
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/* Common status */
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#define RKEP_SMODE_INIT 0
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#define RKEP_SMODE_LNKRDY 1
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#define RKEP_SMODE_LNKUP 2
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#define RKEP_SMODE_ERR 0xff
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/* Firmware download status */
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#define RKEP_SMODE_FWDLRDY 0x10
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#define RKEP_SMODE_FWDLDONE 0x11
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/* Application status*/
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#define RKEP_SMODE_APPRDY 0x20
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struct rkpcie_boot {
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/* magic: "RKEP" */
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u32 magic;
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u32 version;
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struct {
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u16 mode;
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u16 submode;
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} devmode;
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/* Size of ATAGS for cap */
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u32 cap_size;
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struct {
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u8 cmd;
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u8 status;
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/* Error code for current CMD */
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u16 opcode;
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} cmd_status;
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u32 reserved[2];
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/* RK ATAGS, for mem and other info */
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struct tag cap;
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/* offset 0x400 */
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struct rkpcie_cmd cmd;
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};
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static void pcie_inbound_config(void)
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{
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u64 base = PCIE_SNPS_IATU_BASE + 0x100;
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u32 val;
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char i;
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/* BAR0: RKEP_BAR0_ADDR */
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writel(RKEP_BAR0_ADDR, base + PCIE_ATU_CPU_ADDR_LOW);
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writel(0, base + PCIE_ATU_CPU_ADDR_HIGH);
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writel(0, base + PCIE_ATU_UNR_REGION_CTRL1);
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/* PCIE_ATU_UNR_REGION_CTRL2 */
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writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (0 << 8),
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base + PCIE_ATU_UNR_REGION_CTRL2);
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for (i = 0; i < 5; i++) {
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val = readl(base + PCIE_ATU_UNR_REGION_CTRL2);
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if (val & PCIE_ATU_ENABLE)
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break;
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udelay(LINK_WAIT_IATU);
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}
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printep("BAR0: 0x%x\n", RKEP_BAR0_ADDR);
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/* BAR2: RKEP_BAR2_ADDR */
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writel(RKEP_BAR2_ADDR, base + PCIE_ATU_CPU_ADDR_LOW + 0x200);
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writel(0, base + PCIE_ATU_CPU_ADDR_HIGH + 0x200);
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writel(0, base + PCIE_ATU_UNR_REGION_CTRL1 + 0x200);
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writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (2 << 8),
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base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200);
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for (i = 0; i < 5; i++) {
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val = readl(base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200);
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if (val & PCIE_ATU_ENABLE)
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break;
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udelay(LINK_WAIT_IATU);
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}
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printep("BAR2: 0x%x%x\n", 0, RKEP_BAR2_ADDR);
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/* BAR4 is wired reg, no need iATU */
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}
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static int rockchip_pcie_ep_set_bar_flag(void *dbi_base, u32 barno, int flags)
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{
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u32 reg;
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reg = PCI_BASE_ADDRESS_0 + (4 * barno);
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/* Disabled the upper 32bits BAR to make a 64bits bar pair */
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if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
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writel(0, dbi_base + reg + 0x100000 + 4);
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writel(flags, dbi_base + reg);
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if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
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writel(0, dbi_base + reg + 4);
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return 0;
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}
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static void pcie_bar_init(void *dbi_base)
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{
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void *resbar_base;
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writel(0, dbi_base + 0x10);
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writel(0, dbi_base + 0x14);
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writel(0, dbi_base + 0x18);
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writel(0, dbi_base + 0x1c);
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writel(0, dbi_base + 0x20);
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writel(0, dbi_base + 0x24);
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/* Resize BAR0 to support 4M 32bits */
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resbar_base = dbi_base + PCI_RESBAR;
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writel(0xfffff0, resbar_base + 0x4);
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writel(0x2c0, resbar_base + 0x8);
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/* BAR2: 64M 64bits */
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writel(0xfffff0, resbar_base + 0x14);
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writel(0x6c0, resbar_base + 0x18);
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/* BAR4: Fixed for EP wired register, 1M 32bits */
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writel(0xfffff0, resbar_base + 0x24);
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writel(0xc0, resbar_base + 0x28);
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/* Set flags */
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rockchip_pcie_ep_set_bar_flag(dbi_base, 0, PCI_BASE_ADDRESS_MEM_TYPE_32);
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rockchip_pcie_ep_set_bar_flag(dbi_base, 2,
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PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
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rockchip_pcie_ep_set_bar_flag(dbi_base, 4, PCI_BASE_ADDRESS_MEM_TYPE_32);
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/* Close bar1 bar3 bar5 */
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writel(0x0, dbi_base + 0x100000 + 0x14);
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//writel(0x0, dbi_base + 0x100000 + 0x18);
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writel(0x0, dbi_base + 0x100000 + 0x1c);
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//writel(0x0, dbi_base + 0x100000 + 0x20);
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writel(0x0, dbi_base + 0x100000 + 0x24);
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/* Close ROM BAR */
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writel(0x0, dbi_base + 0x100000 + 0x30);
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}
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static void pcie_bar0_header_init(void)
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{
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struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR;
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bh->magic = RKEP_BOOT_MAGIC;
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bh->version = 0x100;
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bh->devmode.mode = RKEP_MODE_LOADER;
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bh->devmode.submode = RKEP_SMODE_INIT;
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bh->cap_size = 0;
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memset((char *)RKEP_BAR0_CMD_ADDR, 0, sizeof(struct rkpcie_cmd));
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}
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static void pcie_link_set_max_speed(void *dbi_base, u32 link_gen)
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{
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u32 cap, ctrl2, link_speed;
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u8 offset = 0x70;
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cap = readl(dbi_base + offset + PCI_EXP_LNKCAP);
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ctrl2 = readl(dbi_base + offset + PCI_EXP_LNKCTL2);
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ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
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link_speed = link_gen;
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cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
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writel(ctrl2 | link_speed, dbi_base + offset + PCI_EXP_LNKCTL2);
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writel(cap | link_speed, dbi_base + offset + PCI_EXP_LNKCAP);
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}
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static void pcie_link_set_lanes(void *dbi_base, u32 lanes)
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{
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u32 val;
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/* Set the number of lanes */
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val = readl(dbi_base + PCIE_PORT_LINK_CONTROL);
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val &= ~PORT_LINK_MODE_MASK;
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switch (lanes) {
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case 1:
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val |= PORT_LINK_MODE_1_LANES;
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break;
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case 2:
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val |= PORT_LINK_MODE_2_LANES;
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break;
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case 4:
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val |= PORT_LINK_MODE_4_LANES;
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break;
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default:
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printf("RKEP: num-lanes %u: invalid value\n", lanes);
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return;
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}
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writel(val, dbi_base + PCIE_PORT_LINK_CONTROL);
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/* Set link width speed control register */
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val = readl(dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
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switch (lanes) {
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case 1:
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val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
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break;
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case 2:
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val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
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break;
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case 4:
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val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
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break;
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}
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val |= PCIE_DIRECT_SPEED_CHANGE;
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writel(val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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}
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static void pcie_devmode_update(int mode, int submode)
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{
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struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR;
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bh->devmode.mode = mode;
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bh->devmode.submode = submode;
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flush_dcache_range(RKEP_BAR0_ADDR, RKEP_BAR0_ADDR + 64);
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}
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#ifdef CONFIG_SPL_RAM_DEVICE
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static void pcie_wait_for_fw(void)
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{
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struct rkpcie_cmd *cmd = (struct rkpcie_cmd *)(RKEP_BAR0_CMD_ADDR);
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int val;
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int i = 0;
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printep("Link ready! Waiting RC to download Firmware:\n");
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printep("Download uboot.img to BAR2+0\n");
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printep("Download boot.img to BAR2+0x400000\n");
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printep("Send CMD_LOADER_RUN to BAR0+0x400\n");
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while (1) {
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invalidate_dcache_range(RKEP_BAR0_CMD_ADDR,
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RKEP_BAR0_CMD_ADDR + 32);
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val = readl(&cmd->cmd);
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if (val == RKEP_CMD_LOADER_RUN)
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break;
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i++;
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if (!(i % 10))
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printep("Waiting for FW, CMD: %x\n", val);
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mdelay(100);
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}
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/* Invalidate Cache for firmware area: BAR2, 64MB */
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invalidate_dcache_range(RKEP_BAR2_ADDR, RKEP_BAR2_ADDR + 0x4000000);
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printep("Firmware Download complete!\n");
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}
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static void pcie_update_atags(void)
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{
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struct tag_ram_partition t_ram_part;
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if (!atags_is_available()) {
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printf("RKEP: No ATAGS data found, create new!\n");
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atags_destroy();
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}
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/* ram partition */
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memset(&t_ram_part, 0, sizeof(t_ram_part));
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t_ram_part.version = 0;
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t_ram_part.count = 1;
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strcpy(t_ram_part.part[0].name, "boot");
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t_ram_part.part[0].start = RKEP_BAR2_ADDR + 0x400000; /* 4M offset */
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t_ram_part.part[0].size = 0x3c00000; /* 60M size */
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atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part);
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}
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void rockchip_pcie_ep_get_firmware(void)
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{
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pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLRDY);
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pcie_wait_for_fw();
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pcie_update_atags();
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pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLDONE);
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}
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#endif
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#ifdef CONFIG_ROCKCHIP_RK3588
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#define BUS_IOC_GPIO3D_IOMUX_SEL_H 0xfd5f807c
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#define GPIO3_BASE 0xfec40000
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#define GPIO3_SWPORT_DR_H (GPIO3_BASE + 0x4)
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#define GPIO3_SWPORT_DDR_H (GPIO3_BASE + 0xc)
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static void pcie_board_init(void)
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{
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/* Enable AU5426 buffer chip on EVB4v10 */
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/* Set GPIO3D4 to gpio output HIGH mode PCIE20_CLK_PWREN */
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writel(0xf << 16, BUS_IOC_GPIO3D_IOMUX_SEL_H);
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writel(0x10001000, GPIO3_SWPORT_DDR_H);
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writel(0x10001000, GPIO3_SWPORT_DR_H);
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udelay(100);
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}
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#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */
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#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */
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#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */
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#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */
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#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */
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#define CRU_BASE_ADDR 0xfd7c0000
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#define CRU_SOFTRST_CON32 (CRU_BASE_ADDR + 0x0a80)
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#define CRU_SOFTRST_CON33 (CRU_BASE_ADDR + 0x0a84)
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#define CRU_SOFTRST_CON34 (CRU_BASE_ADDR + 0x0a88)
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#define CRU_GATE_CON32 (CRU_BASE_ADDR + 0x0880)
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#define CRU_GATE_CON33 (CRU_BASE_ADDR + 0x0884)
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#define CRU_GATE_CON34 (CRU_BASE_ADDR + 0x0888)
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#define CRU_GATE_CON38 (CRU_BASE_ADDR + 0x0898)
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#define CRU_GATE_CON39 (CRU_BASE_ADDR + 0x089c)
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#define PHPTOPCRU_BASE_ADDR 0xfd7c8000
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#define PHPTOPCRU_SOFTRST_CON00 (PHPTOPCRU_BASE_ADDR + 0x0a00)
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#define PHPTOPCRU_GATE_CON00 (PHPTOPCRU_BASE_ADDR + 0x0800)
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#define PCIE3PHY_GRF_BASE 0xfd5b8000
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#define RK3588_PCIE3PHY_GRF_CMN_CON0 (PCIE3PHY_GRF_BASE + 0x0000)
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#define PCIE3PHY_GRF_PHY0_CON6 (PCIE3PHY_GRF_BASE + 0x0118)
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#define PCIE3PHY_GRF_PHY1_CON6 (PCIE3PHY_GRF_BASE + 0x0218)
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#define PCIE3PHY_GRF_PHY0_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x1004)
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#define PCIE3PHY_GRF_PHY0_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x1104)
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#define PCIE3PHY_GRF_PHY1_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x2004)
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#define PCIE3PHY_GRF_PHY1_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x2104)
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#define FIREWALL_PCIE_MASTER_SEC 0xfe0300f0
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#define FIREWALL_PCIE_ACCESS 0xfe586040
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#define CRU_PHYREF_ALT_GATE_CON (CRU_BASE_ADDR + 0x0c38)
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#define PMU_PWR_GATE_SFTCON1 0xfd8d8150
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static void pcie_cru_init(void)
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{
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u32 phy0_mplla, phy1_mplla, t0 = 0, t1 = 0;
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u32 i, timeout = 500;
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/* Enable power domain: PD_PCIE & PD_PHP */
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writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1);
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/* FixMe init 3.0 PHY */
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/* Phy mode: Aggregation NBNB */
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writel((0x7 << 16) | PHY_MODE_PCIE_AGGREGATION, RK3588_PCIE3PHY_GRF_CMN_CON0);
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printep("PHY Mode 0x%x\n", readl(RK3588_PCIE3PHY_GRF_CMN_CON0) & 7);
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/* Enable clock and sfreset for Controller and PHY */
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writel(0xffff0000, CRU_SOFTRST_CON32);
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writel(0xffff0000, CRU_SOFTRST_CON33);
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writel(0xffff0000, CRU_SOFTRST_CON34);
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writel(0xffff0000, CRU_GATE_CON32);
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writel(0xffff0000, CRU_GATE_CON33);
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writel(0xffff0000, CRU_GATE_CON34);
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writel(0xffff0000, CRU_GATE_CON38);
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writel(0xffff0000, CRU_GATE_CON39);
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writel((0x1 << 24), PHPTOPCRU_SOFTRST_CON00);
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writel(0xffff0000, PHPTOPCRU_GATE_CON00);
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/* PHY Reset */
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writel((0x1 << 10) | (0x1 << 26), PHPTOPCRU_SOFTRST_CON00);
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udelay(1);
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#ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
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writel(0x000f0000, CRU_PHYREF_ALT_GATE_CON);
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/* PHY0 & PHY1 use internal clock */
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writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY0_CON6);
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writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY1_CON6);
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/* phy0_rx0_cmn_refclk_mod */
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writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN0_CON1);
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/* phy1_rx0_cmn_refclk_mod */
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writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN1_CON1);
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/* phy0_rx0_cmn_refclk_mod */
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writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN0_CON1);
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/* phy1_rx0_cmn_refclk_mod */
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writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN1_CON1);
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#endif
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udelay(1000);
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/* Deassert PCIe PMA output clamp mode */
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writel((0x1 << 8) | (0x1 << 24), RK3588_PCIE3PHY_GRF_CMN_CON0);
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/* Deassert PHY Reset */
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writel((0x1 << 26), PHPTOPCRU_SOFTRST_CON00);
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/* S-Phy: waiting for phy locked */
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for (i = 0; i < timeout; i++) {
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phy0_mplla = readl(PCIE3PHY_GRF_BASE + 0x904);
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phy1_mplla = readl(PCIE3PHY_GRF_BASE + 0xA04);
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|
if (phy0_mplla != t0 || phy1_mplla != t1) {
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printf("RKEP: GRF:904=%x, a04=%x...\n", phy0_mplla, phy1_mplla);
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t0 = phy0_mplla;
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t1 = phy1_mplla;
|
if (phy0_mplla == 0xF && phy1_mplla == 0xF)
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break;
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}
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udelay(10);
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}
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|
/* PHY config: no config need for snps3.0phy */
|
|
/* Enable PCIe Access in firewall and master secure mode */
|
writel(0xffff0000, FIREWALL_PCIE_MASTER_SEC);
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writel(0x01800000, FIREWALL_PCIE_ACCESS);
|
}
|
#elif CONFIG_ROCKCHIP_RK3568
|
|
static void pcie_board_init(void)
|
{
|
/* to-do */
|
}
|
|
static const u16 phy_fw[] = {
|
#include "./../../../drivers/phy/phy-rockchip-snps-pcie3.fw"
|
};
|
|
#define GRF_PCIE30PHY_RK3568_CON1 0x4
|
#define GRF_PCIE30PHY_RK3568_CON3 0xC
|
#define GRF_PCIE30PHY_RK3568_CON4 0x10
|
#define GRF_PCIE30PHY_RK3568_CON5 0x14
|
#define GRF_PCIE30PHY_RK3568_CON6 0x18
|
#define GRF_PCIE30PHY_RK3568_CON9 0x24
|
#define GRF_PCIE30PHY_RK3568_STATUS0 0x80
|
#define RK3568_SRAM_INIT_DONE(reg) ((reg) & BIT(14))
|
|
#define PMUCRU_BASE 0xFDD00000
|
#define PMUCRU_PMUGATE_CON02 (PMUCRU_BASE + 0x188)
|
|
#define CRU_BASE 0xFDD20000
|
#define CRU_GATE_CON12 (CRU_BASE + 0x330)
|
#define CRU_GATE_CON13 (CRU_BASE + 0x334)
|
#define CRU_GATE_CON33 (CRU_BASE + 0x384)
|
#define CRU_SOFTRST_CON12 (CRU_BASE + 0x430)
|
#define CRU_SOFTRST_CON27 (CRU_BASE + 0x46c)
|
|
#define PCIE30_PHY_GRF 0xFDCB8000
|
|
void pcie_cru_init(void)
|
{
|
u32 i, reg;
|
void __iomem *mmio = (void __iomem *)0xFE8C0000;
|
|
/* Enable phy and controoler clk */
|
writel(0xffff0000, PMUCRU_PMUGATE_CON02);
|
writel(0xffff0000, CRU_GATE_CON12);
|
writel(0xffff0000, CRU_GATE_CON13);
|
writel(0xffff0000, CRU_GATE_CON33);
|
writel(0xffff0000, CRU_SOFTRST_CON27);
|
|
writel(0x40004000, CRU_SOFTRST_CON27);
|
writel(0x80008000, PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9);
|
|
writel((0x1 << 15) | (0x1 << 31),
|
PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram
|
|
#ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
|
/* use internal clock */
|
writel(0x0 | (0x1 << 31), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON3);
|
|
/* rx0_cmn_refclk_mode disabled */
|
writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON5);
|
/* rx1_cmn_refclk_mode disabled */
|
writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON6);
|
#endif
|
|
writel((0x0 << 14) | (0x1 << (14 + 16)),
|
PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done
|
writel((0x0 << 13) | (0x1 << (13 + 16)),
|
PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_bypass
|
|
writel(0x40000000, CRU_SOFTRST_CON27);
|
|
udelay(5);
|
printf("RKEP: sram initial\n");
|
while (1) {
|
reg = readl(PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_STATUS0);
|
if (RK3568_SRAM_INIT_DONE(reg))
|
break;
|
}
|
printf("RKEP: sram init done\n");
|
|
writel((0x3 << 8) | (0x3 << (8 + 16)),
|
PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram
|
for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
|
writel(phy_fw[i], mmio + (i << 2));
|
|
printf("RKEP: snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
|
writel((0x0 << 8) | (0x3 << (8 + 16)),
|
PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9);
|
writel((0x1 << 14) | (0x1 << (14 + 16)),
|
PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done
|
|
writel(0xffff0000, CRU_SOFTRST_CON12);
|
writel(0x100010, PCIE_SNPS_APB_BASE + 0x180);
|
|
udelay(1);
|
}
|
#endif
|
|
static void pcie_ep_init(void)
|
{
|
u32 val;
|
void *dbi_base = (void *)PCIE_SNPS_DBI_BASE;
|
u64 apb_base = PCIE_SNPS_APB_BASE;
|
int i, retries = 0;
|
|
#ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
|
printep("RefClock in SRNS clock mode\n");
|
#else
|
printep("RefClock in common clock_mode\n");
|
#endif
|
|
/*
|
* ltssm_enable enhance mode and enable delaying the link training
|
* after Hot Reset
|
*/
|
writel(0x120012, apb_base + 0x180);
|
|
/* Unmask pm_turnoff_int */
|
writel(0x04000000, apb_base + 0x18);
|
|
/* PortLorgic DBI_RO_WR_EN */
|
val = readl((dbi_base + 0x8bc));
|
val |= 0x1;
|
writel(val, dbi_base + 0x8bc);
|
|
reinit:
|
pcie_bar_init(dbi_base);
|
pcie_inbound_config();
|
|
/* Device PID, DID */
|
writel(0x1d87, dbi_base + 0x00);
|
writel(0x356a, dbi_base + 0x02);
|
/* Device Class: Processing accelerators */
|
writel(0x1200, dbi_base + 0x0a);
|
|
pcie_link_set_max_speed(dbi_base, PCI_EXP_LNKCTL2_TLS_8_0GT);
|
|
#ifdef CONFIG_ROCKCHIP_RK3588
|
pcie_link_set_lanes(dbi_base, 4);
|
#elif CONFIG_ROCKCHIP_RK3568
|
pcie_link_set_lanes(dbi_base, 2);
|
#endif
|
|
/* EP mode */
|
writel(0xf00000, apb_base);
|
udelay(100);
|
|
/* Enable EP mem/io access */
|
val = readl(dbi_base + 0x4);
|
writel(val | 0x6, dbi_base + 0x4);
|
|
if (retries) /* Set app_dly2_done to enable app_ltssm_enable */
|
writel(0x80008, apb_base + 0x180);
|
else /* Enable LTSSM */
|
writel(0xc000c, apb_base);
|
printep("init PCIe fast Link up\n");
|
pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKRDY);
|
|
/* Waiting for Link up */
|
while (1) {
|
val = readl(apb_base + 0x300);
|
if (((val & 0x3ffff) & ((0x3 << 16) | 0x11)) == 0x30011)
|
break;
|
mdelay(1);
|
}
|
printep("Link up %x\n", val);
|
mdelay(3);
|
|
/* Wait for link stable */
|
for (i = 0; i < 10000; i++) {
|
val = readl(apb_base + 0x10);
|
if (val & 0x4) {
|
writel(0x4, apb_base + 0x10);
|
printep("Link is reset, int status misc=%x\n", val);
|
if (retries < 3) {
|
retries++;
|
goto reinit;
|
} else {
|
break;
|
}
|
}
|
udelay(1);
|
}
|
printep("Done\n");
|
pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP);
|
}
|
|
void rockchip_pcie_ep_init(void)
|
{
|
u32 val;
|
|
printf("\nRKEP: Init PCIe EP\n");
|
pcie_bar0_header_init();
|
|
#ifdef CONFIG_ROCKCHIP_RK3588
|
writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1);
|
udelay(10);
|
#endif
|
/* Re-in pcie initial */
|
val = readl(PCIE_SNPS_APB_BASE + 0x300);
|
if (((val & 0x3ffff) & ((0x3 << 16))) == 0x30000) {
|
printf("RKEP: already link up\n");
|
return;
|
}
|
|
pcie_board_init();
|
/* CRU and PHY Init */
|
pcie_cru_init();
|
|
pcie_ep_init();
|
}
|
